ADE7858 datasheet(68/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 68 of 76

-010: gain=4

-011: gain=8

-100: gain=16

-101, 110, 111: reserved. When set, the ADE7858 behaves like PGA1 [2:0]=000

5 to 3

Reserved

000

Reserved. These bits do not manage any functionality.

8 to 6

PGA3[2:0]

000

Phase voltages gain selection

-000: gain=1

-001: gain=2

-010: gain=4

-011: gain=8

-100: gain=16

-101, 110, 111: reserved. When set, the ADE7858 behaves like PGA3 [2:0]=000

15 to 9

Reserved

000 0000

Reserved. These bits do not manage any functionality.

Table 36. CFMODE register (address 0xE610)

Bit

Location

Bit

Mnemonic

Default

value

Description

2-0

CF1SEL[2:0]

000

-000: CF1 frequency proportional to the sum of total active powers on each phase identified by

bits 2-0 (TERMSEL1) in COMPMODE[15:0] register.

-001: CF1 frequency proportional to the sum of total reactive powers on each phase identified by

bits 2-0 (TERMSEL1) in COMPMODE[15:0] register.

-010: CF1 frequency proportional to the sum of apparent powers on each phase identified by bits

2-0 (TERMSEL1) in COMPMODE[15:0] register.

-011,100, 101,110,111: reserved. When set, the ADE7858 behaves like CF1SEL [2:0]=000.

5-3

CF2SEL[2:0]

001

-000: CF2 frequency proportional to the sum of total active powers on each phase identified by

bits 5:3 (TERMSEL2) in COMPMODE[15:0] register.

-001: CF2 frequency proportional to the sum of total reactive powers on each phase identified by

bits 5:3 (TERMSEL2) in COMPMODE[15:0] register.

-010: CF2 frequency proportional to the sum of apparent powers on each phase identified by bits

5:3 (TERMSEL2) in COMPMODE[15:0] register.

-011,100,101,110,111: reserved. When set, the ADE7858 behaves like CF2SEL [2:0]=000.

8-6

CF3SEL[2:0]

010

-000: CF3 frequency proportional to the sum of total active powers on each phase identified by

bits 8:6 (TERMSEL3) in COMPMODE[15:0] register.

-001: CF3 frequency proportional to the sum of total reactive powers on each phase identified by

bits 8:6 (TERMSEL3) in COMPMODE[15:0] register.

-010: CF3 frequency proportional to the sum of apparent powers on each phase identified by bits

8:6 (TERMSEL3) in COMPMODE[15:0] register.

-011,100,101,110,111: reserved. When set, the ADE7858 behaves like CF3SEL [2:0]=000.

CF1DIS

When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency converter

remains enabled even if CF1DIS=1. When set to 0, the CF1 output is enabled.

CF2DIS

When this bit is set to 1, the CF2 output is disabled. The respective digital to frequency converter

remains enabled even if CF2DIS=1. When set to 0, the CF2 output is enabled.

CF3DIS

When this bit is set to 1, the CF3 output is disabled. The respective digital to frequency converter

remains enabled even if CF3DIS=1. When set to 0, the CF3 output is enabled.

CF1LATCH

When this bit is set to 1, the content of the corresponding energy registers is latched when a CF1

pulse is generated. See Synchronizing energy registers with CFx outputs section.

CF2LATCH

When this bit is set to 1, the content of the corresponding energy registers is latched when a CF2

pulse is generated. See Synchronizing energy registers with CFx outputs section.

CF3LATCH

When this bit is set to 1, the content of the corresponding energy registers is latched when a CF3

pulse is generated. See Synchronizing energy registers with CFx outputs section.

Reserved

Reserved. This bit does not manage any functionality.

Table 37. APHCAL, BPHCAL, CPHCAL registers (addresses 0xE614, 0xE615, 0xE616)

Bit

Location

Bit

Mnemonic

Default

value

Description

9-0

PHCALVAL

0000000000

If current channel compensation is necessary, these bits can vary only between 0 and 383.

ADE7858 Datasheet(PDF) 68 Page - Analog Devices

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