ADE7858 datasheet(48/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 48 of 76

Inoload, the minimum rms value of phase current the meter starts

measuring.

VARNOLOAD[23:0] contains usually the same value as

APNOLOAD[23:0]. When APNOLOAD and VARNOLOAD

are set to negative values, the no-load detection circuit is

disabled.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words and the DSP works on 28 bits.

APNOLOAD and VARNOLOAD 24-bit signed registers are

accessed as 32-bit registers with 4 most significant bits padded

with 0s and sign extended to 28 bits. See Figure 15 for details.

Bit 0 (NLOAD) in STATUS1[31:0] register is set when this no-

load condition in one of the three phases is triggered. Bits 2, 1, 0

(NLPHASE[2:0]) in PHNOLOAD[15:0] register indicate the

state of all phases relative to no-load condition and are set

simultaneously with bit NLOAD in STATUS1[31:0].

NLPHASE[0] indicates the state of phase A , NLPHASE[1] the

state of phase B, NLPHASE[2] the state of phase C. When bit

NLPHASE[x], x=0, 1, 2 is cleared to 0, it means the phase is out

of no-load condition. When set to 1, it means the phase is in

no-load condition.

An interrupt attached to the bit 0 (NLOAD) in STATUS1[31:0]

may be enabled by setting bit 0 in MASK1[31:0] register. If

enabled, the

IRQ pin is set low and the status bit is set to 1

whenever one of three phases enters or exits this no-load

condition. To find the phase that triggered the interrupt,

PHNOLOAD[15:0] register is read immediately after reading

STATUS1[31:0]. Then the status bit is cleared and

IRQ pin is

set back high by writing STATUS1 register with the

corresponding bit set to 1.

No-load detection based on apparent power

This no-load condition is triggered when the absolute value of

phase apparent power is less than or equal to the threshold

indicated in VANOLOAD[23:0] 24-bit signed register. In this

case, the apparent energy of that phase is not accumulated and

no CF pulses are generated based on this energy. VANOLOAD

represents the positive no-load level of apparent power relative

to PMAX, the maximum apparent power obtained when full

scale voltages and currents are provided at ADC inputs. The

expression used to compute VANOLOAD[23:0] signed 24-bit

value is:

PMAX

VANOLOAD

noload





where: PMAX=33,516,139=0x1FF6A6B, the instantaneous

apparent power computed when the ADC inputs are at full scale

UFS, IFS, the rms values of phase voltages and currents when the

ADC inputs are at full scale.

Un, the nominal rms value of phase voltage.

Inoload, the minimum rms value of phase current the meter starts

measuring.

When VANOLOAD[23:0] is set to negative values, the no load

detection circuit is disabled.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words and the DSP works on 28 bits. Similar to

registers presented inFigure 15, VANOLOAD 24-bit signed

bits padded with 0s and sign extended to 28 bits.

Bit 2 (VANLOAD) in STATUS1[31:0] register is set when this

no-load condition in one of the three phases is triggered. Bits 8,

7, 6 (VANLPHASE[2:0]) in PHNOLOAD[15:0] register indicate

the state of all phases relative to no-load condition and are set

simultaneously with bit VANLOAD in STATUS1[31:0].

VANLPHASE[0] indicates the state of phase A ,

VANLPHASE[1] the state of phase B, VANLPHASE[2] the state

of phase C. When bit VANLPHASE[x], x=0, 1, 2 is cleared to 0,

it means the phase is out of no-load condition. When set to 1, it

means the phase is in no-load condition.

An interrupt attached to the bit 2 (VANLOAD) in

STATUS1[31:0] may be enabled by setting bit 2 in

MASK1[31:0] register. If enabled, the

IRQ pin is set low and

the status bit is set to 1 whenever one of three phases enters or

exits this no-load condition. To find the phase that triggered the

interrupt, PHNOLOAD[15:0] register is read immediately after

reading STATUS1[31:0]. Then the status bit is cleared and

IRQ pin is set back high by writing STATUS1 register with the

corresponding bit set to 1.

CHECKSUM REGISTER

The ADE7858 has a checksum 32-bit register

CHECKSUM[31:0] that ensures certain very important

configuration registers maintain their desired value during

normal power mode PSM0.

The registers covered by this register are MASK0[31:0],

MASK1[31:0], COMPMODE[15:0], GAIN[15:0],

CFMODE[15:0], CF1DEN[15:0], CF2DEN[15:0],

CF3DEN[15:0], CONFIG[15:0], MMODE[7:0],

ACCMODE[7:0], LCYCMODE[7:0], HSDC_CFG[7:0] and

other six 8-bit reserved internal registers that always have

default values. The ADE7858 computes the cyclic redundancy

check (CRC) based on the IEEE802.3 standard. The registers

are introduced one by one into a linear feedback shift register

(LFSR) based generator starting with the less significant bit (as

presented in Figure 56). The 32-bit result is written in

CHECKSUM[31:0] register. After power up or a

hardware/software reset, the CRC is computed on the default

values of the registers. The result is 0x93D774E6.

Figure 57 presents how LFSR works. Bits a0, a1,…, a255 represent

the bits from the list of registers presented above. a0 is the less

significant bit of the first internal register to enter LFSR, a255 is

the most significant bit of MASK0[31:0] register, the last

presented below:

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