ADE7858 datasheet(70/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 70 of 76

Bit

Location

Bit

Mnemonic

Default

value

Description

SWRST

When this bit is set to 1, a software reset is initiated.

9,8

VTOIA[1:0]

These bits decide what phase voltage is considered together with phase A current in the power

path:

00=phase A voltage

01=phase B voltage

10=phase C voltage

11=reserved. When set, the ADE7858 behaves like VTOIA [1:0]=00

11,10

VTOIB[1:0]

These bits decide what phase voltage is considered together with phase B current in the power

path:

00=phase B voltage

01=phase C voltage

10=phase A voltage

11=reserved. When set, the ADE7858 behaves like VTOIB [1:0]=00

13,12

VTOIC[1:0]

These bits decide what phase voltage is considered together with phase C current in the power

path:

00=phase C voltage

01=phase A voltage

10=phase B voltage

11=reserved. When set, the ADE7858 behaves like VTOIC [1:0]=00

Reserved

Reserved. This bit does not manage any functionality.

Reserved

Reserved. This bit does not manage any functionality.

Table 40. MMODE register (address 0xE700)

Bit

Location

Bit

Mnemonic

Default

value

Description

1,0

PERSEL[1:0]

-00: Phase A selected as source of the voltage line period measurement

-01: Phase B selected as source of the voltage line period measurement

-10: Phase C selected as source of the voltage line period measurement

-11:Reserved. When set, the ADE7858 behaves like PERSEL[1:0]=00

PEAKSEL[0]

PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all 3 phases

simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak measurement period

indicated in PEAKCYC[7:0] register decreases accordingly because zero crossings are detected on

more than one phase.

When this bit is set to 1, phase A is selected for the voltage and current peak registers

PEAKSEL[1]

When this bit is set to 1, phase B is selected for the voltage and current peak registers

PEAKSEL[2]

When this bit is set to 1, phase C is selected for the voltage and current peak registers

7-5

Reserved

000

Reserved. These bits do not manage any functionality.

Table 41. ACCMODE Register (Address 0xE701)

Bit

Location

Bit

Mnemonic

Default

value

Description

1,0

WATTACC[1:0]

-00: signed accumulation mode of the total active powers

-01: reserved. When set, the ADE7858 behaves like WATTACC[1:0]=00

-10: reserved. When set, the ADE7858 behaves like WATTACC[1:0]=00

-11: absolute accumulation mode of the total active powers

3,2

VARACC[1:0]

-00: signed accumulation of the total reactive powers

-01: reserved. When set, the ADE7858 behaves like VARACC[1:0]=00

-10:the total reactive power are accumulated depending on the sign of the total active power:

-if the active power is positive, the reactive power is accumulated as is

-if the active power is negative, the reactive power is accumulated with reversed sign

-11: reserved. When set, the ADE7858 behaves like VARACC[1:0]=00

5,4

CONSEL[1:0]

These bits are used to select the inputs to the energy accumulation registers. IA’, IB’ and IC’ are IA, IB

and IC shifted respectively by -90°.

-00: 3 phase 4 wires with 3 voltage sensors

ADE7858 Datasheet(PDF) 70 Page - Analog Devices

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