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ADE7858 Datasheet(PDF) 38 Page - Analog Devices |
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ADE7858 Datasheet(HTML) 38 Page - Analog Devices |
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38 / 76 page  ADE7858 Preliminary Technical Data Rev. PrA| Page 38 of 76 m k 1 m , k k k m k m k 1 m , k k k m k 1 k k k k k k k 2 t m k cos I V 2 t m k cos I V 2 t k 2 cos 2 cos I V ) t ( q (30) The average total reactive power over an integral number of line cycles (n) is given by the expression in Equation (31). nT 0 1 k k k k k 2 cos I V dt t q nT 1 Q (31) 1 k k k k k sin I V Q where: T is the period of the line cycle. Q is referred to as the total reactive power. Note that the total reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in Equation (30), that is, 1 k k k k k sin I V . This is the relationship used to calculate the total reactive power in the ADE7858 for each phase. The instantaneous reactive power signal q(t) is generated by multiplying each harmonic of the voltage signals by the 90° phase-shifted corresponding harmonic of the current in each phase. The ADE7858 stores the instantaneous total phase reactive powers into AVAR[23:0], BVAR[23:0] and CVAR[23:0] registers. Their expression is: 4 1 k k k FS k FS k 2 1 PMAX sin I I U U xVAR (32) where: x=A, B, C UFS, IFS are the rms values of the phase voltage and current when the ADC inputs are at full scale. PMAX=33,516,139 is the instantaneous power computed when the ADC inputs are at full scale and in phase. The xVAR[23:0], x=A, B, C waveform registers may be accessed using various serial ports. Refer to Waveform Sampling Mode chapter for more details. Reactive Power Gain Calibration The average reactive power from the LPF output in each phase can be scaled by ±100% by writing to the phase’s VAR gain 24-bit register (AVARGAIN[23:0], BVARGAIN[23:0], CVARGAIN[23:0], AFVARGAIN[23:0], BFVARGAIN[23:0] or CFVARGAIN[23:0]). xVARGAIN, x=A,B,C registers are placed in each phase of the total reactive power data path. The VAR gain registers are twos complement, signed registers and have a resolution of 2-23/LSB. The function of the VAR gain registers is expressed by 23 2 gister Gain VAR 1 Output 2 LPF Power Reactive Average Re (33) The output is scaled by –50% by writing 0xC00000 to the VAR gain registers and increased by +50% by writing 0x400000 to them. These registers can be used to calibrate the reactive power (or energy) gain in the ADE7858 for each phase. As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AVARGAIN, BVARGAIN, CVARGAIN 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits. Reactive Power Offset Calibration The ADE7858 provides a VAR offset register on each phase and on each reactive power. AVAROS[23:0], BVAROS[23:0], and CVAROS[23:0] registers compensate the offsets in the total reactive power calculations. These are signed twos complement, 24-bit registers that are used to remove offsets in the reactive power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no reactive power is being consumed. The offset registers’ resolution is the same as the active power offset registers (see the Active Power Offset Calibration section). As previously stated, the serial ports of the ADE7858 work on 32, 16 or 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 15, AVAROS, BVAROS, CVAROS 24-bit signed registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits. Sign of Reactive Power Calculation Note that the reactive power is a signed calculation. Table 14 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation. The ADE7858 has a sign detection circuitry for reactive power calculations. As will be seen in the Reactive Energy Calculation section, the reactive energy accumulation is executed in two stages. Every time a sign change is detected in the energy accumulation at the end of the first stage, that is after the energy accumulated into the 48 bit accumulator reaches VARTHR[47:0] threshold, a dedicated interrupt is triggered. |
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