EVAL-ADE7858EBZ datasheet(29/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 29 of 76

from OVLVL[23:0] register, bit 18 (OV) in STATUS1[31:0] and

bit 9 (OVPHASE[0]) in PHSTATUS[15:0] registers are set to 1.

The bit 18 (OV) of STATUS1[31:0] register and bit 9

(OVPHASE[0]) in PHSTATUS[15:0] register are cancelled

when STATUS1 register is written with bit 18 (OV) set to 1.

The recommended procedure to manage overvoltage events is

the following:

-enable OV interrupts in MASK1[31:0] register by setting bit 18

(OV) to 1.

-when an overvoltage event happens, the

IRQ

interrupt pin

goes low.

-STATUS1[31:0] register is read with bit 18 (OV) set to 1.

-PHSTATUS[15:0] is read, identifying on which phase or

phases an overvoltage event happened.

-STATUS1[31:0] register is written with bit 18 (OV) set to 1. In

this moment, bit OV is erased and also all bits 11, 10, 9

(OVPHASE[2:0]) of PHSTATUS[15:0] register.

In case of an overcurrent event, if bit 17 (OI) in MASK1[31:0]

IRQ

interrupt pin is driven low. In the same

moment, bit 17 (OI) in STATUS1[31:0] register and one of bits

5, 4, 3 (OIPHASE[2:0]) in PHSTATUS[15:0] register identifying

the phase that generated the interrupt are set. To find the phase

that triggered the interrupt, PHSTATUS[15:0] register is read

immediately after reading STATUS1[31:0]. Then the status bit

17 (OI) in STATUS1[31:0] register and bits 5,4,3

(OIPHASE[2:0]) in PHSTATUS[15:0] register are cleared and

IRQ

pin is set back high by writing STATUS1[31:0] register

with the status bit set to 1. The process is similar with the

overvoltage detection.

Overvoltage and Overcurrent Level Set

The content of the overvoltage OVLVL[23:0] and overcurrent

OILVL[23:0] 24-bit unsigned registers is compared to the

absolute value of the voltage and current channels. The

maximum value of these registers is the maximum value of the

HPF outputs: +5,928,256 (0x5A7540). When OVLVL or OILVL

are equal to this value, the overvoltage or overcurrent

conditions will never be detected. Writing 0x0 to these registers

signifies the overvoltage or overcurrent conditions are

continuously detected and the corresponding interrupts are

triggered permanently.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words. Similar to the register presented in Figure

16, OILVL and OVLVL registers are accessed as 32-bit registers

with 8 most significant bits padded with 0s.

PHASE COMPENSATION

As seen in Current Channel ADC and Voltage Channel ADC

chapters, the data path for both current and voltages is the

same. The phase error between current and voltage signals

introduced by the ADE7858 is negligible. However, the

ADE7858 must work with transducers that may have inherent

phase errors. For example, a current transformer (CT) with a

phase error of 0.1° to 3° is not uncommon. These phase errors

can vary from part to part, and they must be corrected to

perform accurate power calculations.

The errors associated with phase mismatch are particularly

noticeable at low power factors. The ADE7858 provides a

means of digitally calibrating these small phase errors. The

ADE7858 allows a small time delay or time advance to be

introduced into the signal processing chain to compensate for

the small phase errors.

The phase calibration registers (APHCAL[9:0], BPHCAL[9:0],

and CPHCAL[9:0]) are 10-bit registers that can vary the time

advance in the voltage channel signal path from +61.5 μs to

−374.0 μs, respectively. Negative values written to the PHCAL

registers represent a time advance, and positive values represent

a time delay. One LSB is equivalent to 0.976 μs of time delay or

time advance (clock rate of 1.024MHz). With a line frequency

of 60 Hz, this gives a phase resolution of 0.0211° (360° × 60

Hz/1.024 MHz) at the fundamental. This corresponds to a total

correction range of −8.079° to +1.329° at 60 Hz. At 50Hz, the

correction range is -6.732° to +1.107° and the resolution is

0.0176°(360° × 50 Hz/1.024 MHz) .

Given a phase error of x degrees measured using the phase

voltage as the reference, then the corresponding LSBs are

computed dividing x by the phase resolution (0.0211°/LSB for

60Hz, 0.0176°/LSB for 50Hz). Only results between -383 and

+63 are acceptable. Numbers outside this range are not

accepted. If the result is negative, the absolute value is written

into PHCAL registers. If the result is positive, 512 is added to it

before writing the result into PHCAL.



















512

resolution

phase

resolution

phase

yPHCAL

(8)

Figure 35 illustrates how the phase compensation is used to

remove x=-1° phase lead in IA of the current channel from the

external current transducer (equivalent of 55.5μs for 50Hz

systems). To cancel the lead (1°) in the current channel of Phase

A, a phase lead must be introduced into the corresponding

voltage channel. Using expression (8), APHCAL is 57, rounded

up from 56.8. The phase lead is achieved by introducing a time

delay of 55.73 μs into the phase A current.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words. As presented in Figure 34, APHCAL,

BPHCAL and CPHCAL 10-bit registers are accessed as a 16-bit

registers with 6 most significant bits padded with 0s.

xPHCAL

0000 00

Figure 34. xPHCAL registers (x=A,B,C) are communicated as 16-bit registers

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