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EVAL-ADE7858EBZ Datasheet(PDF) 44 Page - Analog Devices

Part # EVAL-ADE7858EBZ
Description  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

EVAL-ADE7858EBZ Datasheet(HTML) 44 Page - Analog Devices

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ADE7858
Preliminary Technical Data
Rev. PrA| Page 44 of 76
Register
Description
Register
Description
power
IBWV
Phase B current
BWATT
Phase B active
power
VBWV
Phase B voltage
CWATT
Phase C active
power
ICWV
Phase C current
AVAR
Phase A reactive
power
VCWV
Phase C voltage
BVAR
Phase B reactive
power
AVA
Phase A apparent
power
CVAR
Phase C reactive
power
BVA
Phase B apparent
power
The bit 17 (DREADY) in STATUS0[31:0] register can be used
to signal when the registers mentioned in Table 17 may be read
using I2C or SPI serial ports. An interrupt attached to the flag
may be enabled by setting bit 17 (DREADY) in MASK0[31:0]
register. See Digital Signal Processor chapter for more details on
bit DREADY.
The ADE7858 contains a High Speed Data Capture (HSDC)
port that is specially designed to provide fast access to the
waveform sample registers. Read HSDC Interface section for
more details.
As previously stated, the serial ports of the ADE7858 work on
32, 16 or 8-bit words. All registers listed in Table 17 are
transmitted signed extended from 24 to 32 bits (see Figure 18).
ENERGY TO FREQUENCY CONVERSION
The ADE7858 provides 3 frequency output pins: CF1, CF2 and
CF3.
CF3 pin is multiplexed with HSCLK pin of HSDC interface.
When HSDC is enabled, the CF3 functionality is disabled at the
pin. CF1 and CF2 pins are always available. After initial
calibration at manufacturing, the manufacturer or end
customer verifies the energy meter calibration. One convenient
way to verify the meter calibration is to provide an output
frequency proportional to the active, reactive or apparent
powers under steady load conditions. This output frequency
can provide a simple, single-wire, optically isolated interface to
external calibration equipment. Figure 49 illustrates the energy-
to-frequency conversion in the ADE7858.
Instantaneous
phase A active
power
Digital Signal Processor
TERMSELx bits in
COMPMODE
CFxSEL bits in
CFMODE
WATT
VAR
VA
Freq Divider
CFxDEN
CFx pulse
output
Instantaneous
phase B active
power
Instantaneous
phase C active
power
ACCUMULATOR
WTHR[47:0]
x
27
x
27
REVPSUMx bit of
STATUS0[31:0]
Figure 49. ADE7858 Energy to Frequency Conversion
The DSP computes the instantaneous values of all phase
powers: total active, total reactive and apparent. The process in
which the energy is sign accumulated in various hr registers
(watt-hr, var-hr and VA-hr) has already been described in
Energy Calculation chapters. In the energy to frequency
conversion process, the instantaneous powers are used to
generate signals at frequency output pins CF1, CF2 and CF3.
One digital to frequency converter is used for every CF pin.
Every converter sums certain phase powers and generates a
signal proportional to the sum. Two sets of bits decide what
powers are converted.
First, bits 2, 1, 0 (TERMSEL1[2:0]), 5, 4, 3 (TERMSEL2[2:0])
and 8, 7, 6 (TERMSEL3[2:0]) of COMPMODE[15:0] register
decide which phases or which combination of phases are added.
TERMSEL1 bits refer to CF1 pin, TERMSEL2 bits refer to CF2
pin and TERMSEL3 bits refer to CF3 pin. TERMSELx[0] bits,
x=1, 2, 3 manage phase A. When set to 1, phase A power is
included in the sum of powers at CFx converter. When cleared
to 0, phase A power is not included. TERMSELx[1] bits manage
phase B, TERMSELx[2] bits manage phase C. Setting all
TERMSELx bits to 1 means all 3 phase powers are added at CFx
converter. Clearing all TERMSELx bits to 0 means no phase
power is added and no CF pulse is generated.
Second, bits 2, 1, 0 (CF1SEL[2:0]), 5, 4, 3 (CF2SEL[2:0]) and 8,
7, 6 (CF3SEL[2:0]) in CFMODE[15:0] register decide what type
power is used at the inputs of CF1, CF2 and respective CF3
converters. Table 18 shows the values that CFxSEL may have:
total active, total reactive or apparent powers.
By default, TERMSELx bits are all 1 and CF1SEL bits are 000,
CF2SEL bits are 001 and CF3SEL bits are 010. This means that
by default, the CF1 digital to frequency converter produces
signals proportional to the sum of all 3 phase total active



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