EVAL-ADE7858EBZ datasheet(46/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 46 of 76

CF1 pulse based on

phase A and phase

B apparent powers

CFCYC=2

AVAHR, BVAHR, CVAHR latched

Energy registers reset

AVAHR, BVAHR, CVAHR latched

Energy registers reset

Figure 51.Synchronizing AVAHR and BVAHR with CF1

Bits 14, 13, 12 (CF3LATCH, CF2LATCH and CF1LATCH) of

CFMODE[15:0] register enable this process when set to 1.

When cleared to 0, the default state, no latch occurs. The

process is available even if the CFx output is not enabled by

CFxDIS bits in CFMODE[15:0].

CF outputs for various accumulation modes

The bits 1, 0 (WATTACC[1:0]) in ACCMODE[7:0] register

determine the accumulation modes of the total active powers

when signals proportional to the active powers are chosen at

CFx pins (bits CFxSEL[2:0], x=1,2,3 in CFMODE[15:0] register

are equal to 000). When WATTACC[1:0]=00, the default value,

the active powers are sign accumulated before entering the

energy to frequency converter. Figure 52 presents the way

signed active power accumulation works. Note that in this

mode, the CF pulses are perfectly synchronized with the active

energy accumulated in watt-hr registers because the powers are

sign accumulated in both data paths.

REVAPx bit

in STATUS0

POS

ACTIVE

POWER

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

ACTIVE

ENERGY

xWSIGN bit

in PHSIGN

APNOLOAD

SIGN=POSITIVE

NEG

POS

NEG

Figure 52. Active power signed accumulation mode

When WATTACC[1:0]=11, the active powers are accumulated

in absolute mode. When the powers are negative, they change

sign and are accumulated together with the positive power.

Figure 53 presents the way absolute active power accumulation

works. Note that in this mode, the watt-hr registers continue to

accumulate active powers in signed mode, even if the CF pulses

are generated based on the absolute accumulation mode.

The bits 3, 2 (VARACC[1:0]) in ACCMODE[7:0] register

determine the accumulation modes of the total and

fundamental reactive powers when signals proportional to the

reactive powers are chosen at CFx pins (bits CFxSEL[2:0], x=1,

2, 3 in CFMODE[15:0] register are equal to 001 or to 100).

When VARACC[1:0]=00, the default value, the reactive powers

are sign accumulated before entering the energy to frequency

converter. Figure 54 presents the way signed reactive power

accumulation works. Note that in this mode, the CF pulses are

perfectly synchronized with the reactive energy accumulated in

var-hr registers because the powers are sign accumulated in

both data paths.

APNOLOAD

SIGN=POSITIVE

REVAPx bit

in STATUS0

xWSIGN bit

in PHSIGN

ACTIVE

POWER

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

ACTIVE

ENERGY

POS

NEG

POS

NEG

Figure 53. Active power absolute accumulation mode

REVRPx bit

in STATUS0

xVARSIGN bit

in PHSIGN

REACTIVE

POWER

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

REACTIVE

ENERGY

POS

VARNOLOAD

SIGN=POSITIVE

NEG

POS

NEG

Figure 54. Reactive power signed accumulation mode

EVAL-ADE7858EBZ Datasheet(PDF) 46 Page - Analog Devices

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