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EVAL-ADE7858EBZ Datasheet(PDF) 36 Page - Analog Devices

Part # EVAL-ADE7858EBZ
Description  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

EVAL-ADE7858EBZ Datasheet(HTML) 36 Page - Analog Devices

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ADE7858
Preliminary Technical Data
Rev. PrA| Page 36 of 76
24 bit unsigned number
0000 0000
0
23
24
31
0
23
24
47
WTHR[47:0]
24 bit signed number
0000 0000
0
23
24
31
WTHR0[31:0]
WTHR1[31:0]
Figure 43. WTHR[47:0] is communicated as two 32-bit registers
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
expression (24).


0
0
T
Lim
n
T
nT
p
dt
t
p
Energy
(24)
where:
n
is the discrete time sample number.
T
is the sample period.
In the ADE7858, the total phase active powers are accumulated
in AWATTHR[31:0], BWATTHR[31:0] and CWATTHR[31:0]
32-bit signed registers. The active energy register content can
roll over to full-scale negative (0x80000000) and continue
increasing in value when the active power is positive.
Conversely, if the active power is negative, the energy register
would underflow to full-scale positive (0x7FFFFFFF) and
continue decreasing in value.
Bit 0 (AEHF) in STATUS0[31:0] register is set when bit 30 of
one of xWATTHR, x=A, B, C registers changes, signifying one
of these registers is half full. If the active power is positive, the
watt-hr register becomes half full when it increments from
0x3FFF FFFF to 0x4000 0000. If the active power is negative,
the watt-hr register becomes half full when it decrements from
0xC000 0000 to 0xBFFF FFFF.
Setting bit 0 in MASK0[31:0] register enables the AEHF
interrupt. If enabled, the
0
IRQ pin is set low and the status bit
is set to 1 whenever one of the energy registers xWATTHR (for
AEHF interrupt), x=A,B,C becomes half full. The status bit is
cleared and
0
IRQ pin is set to logic high by writing STATUS0
register with the corresponding bit set to 1.
Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a
read-with-reset for all watt-hr accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register
is 125μs (1/8KHz). With full-scale sinusoidal signals on the
analog inputs and the watt gain registers set to 0x00000, the average
word value from each LPF2 is PMAX=33,516,139=0x1FF6A6B.
If the WTHR[47:0] threshold is set at PMAX level, this means
the DSP generates a pulse that is added at watt-hr registers
every 125 μs.
The maximum value that can be stored in the watt-hr
accumulation register before it overflows is 231 − 1 or
0x7FFFFFFF. The integration time is calculated as
s
55
min
33
h
74
s
125
FFFF
,
FFF
7
x
0
Time
(25)
Energy Accumulation Modes
The active power accumulated in each watt-hr accumulation
32-bit register (AWATTHR, BWATTHR, CWATTHR) depends
on the configuration of bits 5, 4 (CONSEL) in ACCMODE[7:0]
register. The different configurations are described in Table 12.
Table 12. Inputs to Watt-Hr Accumulation Registers
CONSEL
AWATTHR
BWATTHR
CWATTHR
00
VA × IA
VB × IB
VC × IC
01
VA × IA
0
VC × IC
10
VA × IA
VB × IB
VB = −VA − VC
VC × IC
11
VA × IA
VB × IB
VB = −VA
VC × IC
Depending on the poly-phase meter service, the appropriate
formula should be chosen to calculate the active energy. The
American ANSI C12.10 Standard defines the different
configurations of the meter. Table 13 describes which mode
should be chosen in these different configurations.
Table 13. Meter Form Configuration
ANSI Meter Form
CONSEL
5S/13S
3-Wire Delta
01
6S/14S
4-Wire Wye
10
8S/15S
4-Wire Delta
11
9S/16S
4-Wire Wye
00
Bits 1, 0 (WATTACC[1:0]) in ACCMODE[7:0] register
determine how CF frequency output may be generated function
of the total and fundamental active powers. While the watt-hr
accumulation registers accumulate the active power in a signed
format, the frequency output may be generated in signed mode
or in absolute mode, function of WATTACC[1:0]. See Energy
to Frequency Conversion chapter for details.
Line Cycle Active Energy Accumulation Mode
In line cycle energy accumulation mode, the energy accumula-
tion is synchronized to the voltage channel zero crossings so
that active energy is accumulated over an integral number of
half line cycles. The advantage of summing the active energy
over an integer number of line cycles is that the sinusoidal
component in the active energy is reduced to 0. This eliminates
any ripple in the energy calculation and allows the energy to be
accumulated accurately over a shorter time. By using the line
cycle energy accumulation mode, the energy calibration can be
greatly simplified, and the time required to calibrate the meter
can be significantly reduced. In line cycle energy accumulation
mode, the ADE7858 transfers the active energy accumulated in
the 32-bit internal accumulation registers into
xWATHHR[31:0], x=A,B,C registers after an integral number of



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