EVAL-ADE7858EBZ datasheet(55/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 55 of 76

Bit Location

Bit Mnemonic

Default Value

Description

VCWV and one 32-bit word always equal to 0

-10= HSDC transmits 9 instantaneous values of phase powers: AVA, BVA, CVA, AWATT,

BWATT, CWATT, AVAR, BVAR and CVAR

-11=reserved. If set, the ADE7858 behaves as if HXFER[1:0]=00.

HSAPOL

-0: HSACTIVE output pin is active LOW.

-1: HSACTIVE output pin is active HIGH

7,6

Reserved. These bits do not manage any functionality.

Bit 5 (HSAPOL) determines the polarity of HSA pin during the

communication. When HSAPOL is 0, the default value, the

HSA pin is active low during the communication. This means

that HSA stays high when no communication is in progress.

When the communication starts, HSA goes low and stays low

until the communication ends. Then it goes back high. When

HSAPOL is 1, the HSA pin is active high during the

communication. This means that HSA stays low when no

communication is in progress. When the communication starts,

HSA goes high and stays high until the communication ends.

Then it goes back low.

Bits 7,6 of HSDC_CFG are reserved. Any value written into

these bits does not have any consequence on HSDC behavior.

Figure 66 shows the HSDC transfer protocol for HGAP=0,

HXFER[1:0]=00 and HSAPOL=0. Note that the HSDC

interface sets a bit on HSD line every HSCLK high to low

transition and the value of bit HSIZE is irrelevant.

Figure 67 shows the HSDC transfer protocol for HSIZE=0,

HGAP=1, HXFER[1:0]=00 and HSAPOL=0. Note that HSDC

interface introduces a 7 HSCLK cycles gap between every 32-bit

word.

Figure 68 shows the HSDC transfer protocol for HSIZE=1,

HGAP=1, HXFER[1:0]=00 and HSAPOL=0. Note that HSDC

interface introduces a 7 HSCLK cycles gap between every 8-bit

word.

Table 20 presents the time it takes to execute an HSDC data

transfer for all HSDC_CFG[7:0] settings. For some settings, the

transfer time is less than 125usec (8KHz), the waveform sample

registers update rate. This means the HSDC port transmits data

every sampling cycle. For settings in which the transfer time is

greater than 125usec, the HSDC port transmits data only in the

first of two consecutive 8KHz sampling cycles. This means it

transmits registers at an effective rate of 4KHz.

Table 20. Communication times for various HSDC settings

HXFER[1:0]

HGAP

HSIZE

HCLK

Comm Time [μsec]

128

77.125

154.25

119.25

238.25

33.25

66.5

51.625

103.25

66.625

133.25

VAWV(32bit)

IBWV(32bit)

CVAR(32bit)

HSD

IAVW (32bit)

HSCLK

HSA

Figure 66. HSDC communication for HGAP=0, HXFER[1:0]=00 and HSAPOL=0. HSIZE is irrelevant

EVAL-ADE7858EBZ Datasheet(PDF) 55 Page - Analog Devices

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