EVAL-ADE7858EBZ datasheet(54/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 54 of 76

HSDC Interface

The High Speed Data Capture (HSDC) interface is disabled

after default. It can be used only if the ADE7858 is configured

with I2C interface. The SPI interface cannot be used in

conjunction with HSDC. Bit 6 (HSDCEN) in CONFIG[15:0]

to 0, the default value, the HSDC interface is disabled. Setting

bit HSDCEN to 1 when SPI is in usage does not have any effect.

HSDC is an interface that is used to send to an external device,

usually a microprocessor or a DSP, up to fifteen 32-bit words.

The words represent the instantaneous values of the phase

currents and voltages, active, reactive and apparent powers. The

registers being transmitted are: IAWV[23:0], VAWV[23:0],

IBWV[23:0], VBWV[23:0], ICWV[23:0], VCWV[23:0],

AVA[23:0], BVA[23:0], CVA[23:0], AWATT[23:0],

BWATT[23:0], CWATT[23:0], AVAR[23:0], BVAR[23:0] and

CVAR[23:0]. All are 24-bit registers that are sign extended to

32-bits (see Figure 18 for details). HSDC can be interfaced with

SPI or similar interfaces.

HSDC is always a master of the communication and consists in

3 pins: HSA, HSD and HSCLK. HSA represents the select

signal. It stays active low or high when a word is transmitted

and is usually connected to the select pin of the slave. HSD is

used to send data to the slave and is usually connected to the

data input pin of the slave. HSCLK is the serial clock line. It is

generated by the ADE7858 and is usually connected to the

serial clock input of the slave. Figure 65 presents the

connections between ADE7858 HSDC and slave devices

containing SPI interface.

The HSDC communication is managed by the

HSDC_CFG[7:0] register (see Table 19). It is recommended to

set HSDC_CFG register to the desired value before enabling the

port using bit 6 (HSDCEN) in CONFIG[15:0] register. In this

way, the state of various pins belonging to HSDC port do not

take levels inconsistent with the desired HSDC behaviour. After

a hardware reset or after power up, the pins MISO/HSD and

/HSA are set high.

Bit 0 (HCLK) in HSDC_CFG[7:0] register determines the serial

clock frequency of the HSDC communication. When HCLK is

0, the default value, then the clock frequency is 8MHz. When

HCLK is 1, the clock frequency is 4MHz. A bit of data is

transmitted for every HSCLK high to low transition. The slave

device that receives data from HSDC samples HSD line on the

low to high transition of HSCLK.

ADE7858

HSD

HSCLK

HSA

SPI

device

MISO

SCK

Figure 65. Connecting ADE7858 HSDC with an SPI

The words may be transmitted as 32-bit packages or as 8-bit

packages. When bit 1 (HSIZE) in HSDC_CFG[7:0] register is 0,

the default value, the words are transmitted as 32-bit packages.

When bit HSIZE is 1, the registers are transmitted as 8-bit

packages. HSDC interface transmits the words with MSB first.

Bit 2 (HGAP) introduces a gap of 7 HSCLK cycles between

packages when is set to 1. When bit HGAP is cleared to 0, the

default value, no gap is introduced between packages and the

communication time is shortest. In this case, HSIZE does not

have any influence on the communication and a bit is put on

HSD line every HSCLK high to low transition.

Bits 4,3 (HXFER[1:0]) decide how many words are transmitted.

When HXFER[1:0] is 00, the default value, then all fifteen

words are transmitted. When HXFER[1:0] is 01, then only the

words representing the instantaneous values of phase currents

and phase voltages are transmitted in the following order:

IAWV, VAWV, IBWV, VBWV, ICWV, VCWV and one 32-bit

word that is always equal to 0. When HXFER[1:0] is 10, then

only the instantaneous values of phase powers are transmitted

in the following order: AVA, BVA, CVA, AWATT, BWATT,

CWATT, AVAR, BVAR and CVAR. The value 11 for

HXFER[1:0] is reserved and writing it is equivalent to writing

00, the default value.

Table 19. HSDC_CFG register

Bit Location

Bit Mnemonic

Default Value

Description

HCLK

-0: HSCLK is 8MHz

-1: HSCLK is 4MHz

HSIZE

-0: HSDC transmits the 32bit registers in 32bit packages, most significant bit first.

-1: HSDC transmits the 32bit registers in 8bit packages, most significant bit first.

HGAP

-0: no gap is introduced between packages.

-1: a gap of 7 HCLK cycles is introduced between packages.

4,3

HXFER[1:0]

-00=HSDC transmits 16 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV,

ICWV, VCWV, one 32-bit word always equal to 0 , AVA, BVA, CVA, AWATT, BWATT, CWATT,

AVAR, BVAR and CVAR

-01= HSDC transmits six instantaneous values of currents and voltages plus one 32-bit

word that is always equal to 0 in the following order: IAWV, VAWV, IBWV, VBWV, ICWV,

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