Analog Integrated Circuit Device Data

10

Freescale Semiconductor

34825

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

13.5

-

-

-

-

8.8

ms

SCL Clock Frequency

-

-

400

kHz

Bus Free Time between a STOP and START Condition

1.3

-

-

Hold Time Repeated START Condition

0.6

-

-

Low Period of SCL Clock

1.3

-

-

High Period of SCL Clock

0.6

-

-

Setup Time for a Repeated START condition

0.6

-

-

Data Hold Time

0

-

-

Data Setup Time

100

-

-

ns

Rising Time of Both SDA and SCL Signals

-

-

ns

Falling Time of Both SDA and SCL Signals

-

-

ns

Setup Time for STOP Condition

0.6

-

-

Input Deglitch Time (for Both Rising and Falling Edges)

55

-

300

ns

Notes

2.

The protection delay is defined as the interval between VBUS voltage rising above the OVP rising threshold, and the OUT pin voltage

dropping below the OVP rising threshold voltage for a VBUS ramp rate of >1.0 V/

3.

The OVP deglitch timer is only for the falling edge threshold.

4.

These parameters are not tested. They are guaranteed by design.

Table 4. Dynamic Electrical Characteristics

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit