MPC8548E datasheet(123/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

123

Clocking

19 Clocking

This section describes the PLL configuration of the MPC8548E. Note that the platform clock is identical

to the core complex bus (CCB) clock.

19.1

Clock Ranges

Table 71 through Table 73 provide the clocking specifications for the processor cores and Table 74,

through Table 76 provide the clocking specifications for the memory bus.

SD_IMP_CAL_TX

AB26

100

Ω (±1%)

to GND

—

SD_PLL_TPA

U26

AVDD_SRDS

Note: All note references in this table use the same numbers as those for Table 67. The reader should refer to Table 67 for the

meanings of these notes.

Table 71. Processor Core Clocking Specifications (MPC8548E and MPC8547E)

Characteristic

Maximum Processor Core Frequency

Unit

Notes

1000 MHz

1200 MHz

1333 MHz

Min

Max

Min

Max

Min

Max

e500 core processor frequency

800

1000

800

1200

800

1333

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 72. Processor Core Clocking Specifications (MPC8545E)

Characteristic

Maximum Processor Core Frequency

Unit

Notes

800 MHz

1000 MHz

1200 MHz

Min

Max

Min

Max

Min

Max

e500 core processor frequency

800

1000

800

1200

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 70. MPC8543E Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

MPC8548E Datasheet(PDF) 123 Page - Freescale Semiconductor, Inc

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