DM9003 datasheet(3/65 Pages) DAVICOM

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DM9003

2-port Switch with Processor Interface

Preliminary datasheet

DM9003-15-DS-P05

April 9, 2009

6.5 RX Status Register (06H) .............................................................................................................................. 18

6.6 Receive Overflow Counter Register (07H) .................................................................................................. 18

6.7 Flow Control Register (0AH)......................................................................................................................... 18

6.8 EEPROM & PHY Control Register (0BH) ..................................................................................................... 18

6.9 EEPROM & PHY Address Register (0CH) ................................................................................................... 19

6.10 EEPROM & PHY Data Registers (0DH~0EH)............................................................................................. 19

6.11 Link Change Control Register (0FH) ......................................................................................................... 19

6.12 Processor Port Physical Address Registers (10H~15H) ......................................................................... 19

6.13 Processor Port Multicast Address Registers (16H~1DH)........................................................................ 19

6.14 RX Packet Length Low Register ( 20H ) .................................................................................................... 20

6.15 RX Packet Length High Register ( 21H ) ................................................................................................... 20

6.16 RX Additional Status Register ( 26H ) ....................................................................................................... 20

6.17 RX Additional Control Register ( 27H )...................................................................................................... 20

6.18 Vendor ID Registers (28H~29H) ................................................................................................................. 20

6.19 Product ID Registers (2AH~2BH) ............................................................................................................... 20

6.20 Chip Revision Register (2CH) .................................................................................................................... 20

6.21 Transmit Check Sum Control Register (31H) ........................................................................................... 20

6.22 Receive Check Sum Control Status Register (32H)................................................................................. 21

6.23 uP Data Bus driving capability Register (38H) ......................................................................................... 21

6.24 IRQ Pin Control Register (39H) .................................................................................................................. 21

DM9003 Datasheet(PDF) 3 Page - Davicom Semiconductor, Inc.

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