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MAX11047 Datasheet(PDF) 15 Page - Maxim Integrated Products |
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MAX11047 Datasheet(HTML) 15 Page - Maxim Integrated Products |
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15 / 18 page ![]() 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ______________________________________________________________________________________ 15 Typical Application Circuits Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst- case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function for an SAR ADC. For example, -0.9 LSB guaran- tees no missing code while -1.1 LSB results in missing code. Offset Error For the MAX11047/MAX11048/MAX11049, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x8000 to 0x8001 for two’s complement encoding. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (5/4.096) x VREF/65,536 above GND. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transi- tion and the ideal analog input of 0.5 x (5/4.096) x VREF/65,536 above GND, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, sub- tracted from the ideal change in analog input voltage on (5/4.096) x VREF x (65,534/65,536). For the MAX11047/MAX11048/MAX11049, top code transition is 0x7FFE to 0x7FFF in two’s complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two’s comple- ment mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11047/MAX11048/MAX11049, the analog input voltage to produce these code transitions is measured and the gain error is computed by sub- tracting (5/4.096) x VREF x (65,534/65,536) from this measurement. 0 FS/2 7FFF 0001 0000 8000 8001 FFFE INPUT VOLTAGE (LSB) FFFF FULL-SCALE TRANSITION +FS 7FFE LSB = FS 65536 FS = 5 x VRDC 4.096 CODE = - 32768, VIN x 65536 VRDC x 4.096 5 Figure 8. Two’s Complement Transfer Function FULL-SCALE TRANSITION FFFF 8001 8000 0000 0001 7FFE INPUT VOLTAGE (LSB) 7FFF FS/2 0 +FS FFFE LSB = FS 65536 FS = 5 x VRDC 4.096 CODE = , VIN x 65536 VRDC x 4.096 5 Figure 9. Offset-Binary Transfer Function |
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