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MPC8323EEC Datasheet(PDF) 80 Page - Freescale Semiconductor, Inc

Part # MPC8323EEC
Description  PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications
PDF  82 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8323EEC Datasheet(HTML) 80 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
80
Freescale Semiconductor
Document Revision History
25.2
Part Marking
Parts are marked as in the example shown in Figure 46.
Figure 46. Freescale Part Marking for PBGA Devices
26 Document Revision History
Table 67 provides a revision history for this hardware specification.
Table 67. Document Revision History
Rev.
No.
Date
Substantive Change(s)
3
12/2009
• Removed references for note 4 from Table 1.
• Added Figure 2 in Section 2.1.2, “Power Supply Voltage Specification.
• Added symbol TA in Table 2.
• Added footnote 2 in Table 2.
• Added a note in Section 4, “Clock Input Timing for rise/fall time of QE input pins.
• Modified CLKIN, PCI_CLK rise/fall time parameters in Table 8. Modified min value of tMCK in Table 19.
• Modified Figure 43.
• Modified formula for ce_clk calculation in Section 22.3, “System Clock Domains.
• Added a note in Section 22.4, “System PLL Configuration.
• Removed the signal ECID_TMODE_IN from Table 55.
• Removed all references of RST signals from Table 55.
2
4/2008
• Removed Figures 2 and 3 overshoot and undershoot voltage specs from Section 2.1.2, “Power Supply
Voltage Specification,” and footnotes 4 and 5 from Table 1.
• Corrected QUIESCE signal to be an output signal in Table 55.
• Added column for GVDD (1.8 V) - DDR2 - to Table 6 with 0.212-W typical power dissipation.
• Added Figure 4 DDR input timing diagram.
• Removed CE_TRB* and CE_PIO* signals from Table 55.
• Added three local bus AC specifications to Table 30 (duty cycle, jitter, delay between input clock and
local bus clock).
• Added row in Table 2 stating junction temperature range of 0 to 105°C.
• Modified Section 2.2, “Power Sequencing,” to include PORESET requirement.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
PBGA
*MMMMM
YWWLAZ
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.



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