Electronic Components Datasheet Search
  English  ▼

X  

WM8148 Datasheet(PDF) 41 Page - Wolfson Microelectronics plc

Part # WM8148
Description  12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser
PDF  43 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8148 Datasheet(HTML) 41 Page - Wolfson Microelectronics plc

Back Button WM8148 Datasheet HTML 35Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 36Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 37Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 38Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 39Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 40Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 41Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 42Page - Wolfson Microelectronics plc WM8148 Datasheet HTML 43Page - Wolfson Microelectronics plc  
Zoom Inzoom in Zoom Outzoom out
 41 / 43 page
background image
WM8148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
41
COLOUR 3 OUTPUT
S
E
N
S
O
R
BUFFER
WM8148
Including
recommended
external
components
SYSTEM
ASIC
BUFFER
BUFFER
DATA
CONTROL I/F
CLOCKS
R
G
B
RINP
GINP
BINP
C
R
C
G
C
B
See sensor
datasheet for
details.
SENSOR TIMING
Maximum Pixel Rate = 4Mpixels/second (Modes 0 and 8)
Figure 47 Block Diagram of Colour CCD Application
REGISTER
SETTING
DESCRIPTION
ADDRESS
HEX
BINARY
NOTE
Set-up register 1
000001
01
0000 0001
MODE: Mode 0: Three-channel CDS
(8-phase)
SELEN, EN: fully enabled
Set-up register 2
000010
00
0000 0000
Default (don’t care)
Set-up register 3
000011
04
0000 0100
RESREF: reset sample half-way
between video samples
Set-up register 4
000101
80
1000 0000
INVOP: invert digital output
(White = 4095)
Coarse offsets
000110
4B
0100 1011
PGAFS: ADC set up for negative
polarity video
RLCEXT, RLCV: internal VRLC
voltage, set to 3.7V
Table 13 Typical Control Register Settings for Figure 47
(CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 8)
REGISTER
SETTING
DESCRIPTION
ADDRESS
HEX
BINARY
NOTE
Set-up register 1
000001
81
1000 0001
MODE: Mode 8: Three-channel CDS
(12-phase)
SELEN, EN: fully enabled
Set-up register 2
000010
00
0000 0000
Default (don’t care)
Set-up register 3
000011
06
0000 0110
RESREF: reset sample half-way
between video samples
Set-up register 4
000101
80
1000 0000
INVOP: invert digital output
(White = 4095)
Coarse offsets
000110
4B
0100 1011
PGAFS: ADC set up for negative
polarity video
RLCEXT, RLCV: internal VRLC
voltage, set to 3.7V
Table 14 Typical Control Register Settings for Figure 47
(CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 12)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com