WM8148 datasheet(16/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

INPUT SAMPLING MODES

To suit different sensors and applications, the WM8148 can sample one, two, or three channels

simultaneously, at the rate of the VSMP clock. In each case there are two possible ratios of VSMP

frequency to the MCLK master clock frequency, and a choice of whether to use CDS. Table 1

summarises the options available, including the respective maximum sample rates. The mode of

operation is set by the Control Register bits MODE[3:0] as shown. Note MODE[0] defines whether or

not CDS is activated.

MAX

SAMPLE

RATE PER

CHANNEL

(VSMP)

MCLK/VSMP

FREQUENCY

RATIO

MAX MCLK

FREQENCY

MAX

OUTPUT

RATE

MODE

NUMBER

(MODE[3:0])

MSPS

MHz

MSPS

CDS

NON-

CDS

Three-channel

(8-phase)

Three-channel

(12-phase)

412

Two-channel

(6-phase)

5.33

10.66

Two-channel

(8-phase)

One-channel

CDS

6.66

N/A

One-channel

non-CDS

N/A

Table 1 Modes of Operation

If an external VSMP signal is not available, the WM8148 can be configured to output a

synchronisation pulse to the system by setting control bit FREE. The internally generated signal is

presented on the VSMP and/or SDO pins depending on the settings of the control bits VSMPOP and

SDO[1:0].

CORRELATED DOUBLE SAMPLING (CDS)

The input signal can be sampled in two ways: Correlated Double Sampling (CDS), or non-CDS.

CDS operation is summarised in Figure 15. The video signal processed is the difference between the

voltage applied at the RINP input when RS turns off and the voltage at the RINP input when VS turns

off, i.e. the difference between reset and video levels from the same pixel of the input signal. This

method of sampling is recommended as it removes common-mode noise.

Figure 15 CDS Reset and Video Level Sampling

In non-CDS modes, RS and VS occur simultaneously. VS samples the video signal, while RS samples

the reference level applied to the VRLC pin. The video signal processed is the difference between

these samples (VRS-VVS). The voltage (VVRLC), on pin VRLC, may be driven externally or internally by

the RLC DAC. In these modes d.c. variations of the input signal are not rejected.

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