WM8148 datasheet(36/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

CONTROL

BIT/WORD

DEFAULT

DESCRIPTION

MUXOP

Changes the data output format from 12-bit parallel to 2 x 8 bit multiplexed.

MUXOP

12-bit wide parallel data

8-bit wide multiplexed data

INVOP

Digitally inverts the polarity of output data.

INVOP

Negative-going video gives negative-going output data

Negative-going video gives positive-going output data

Coarse Offsets

Address

000110

RLCV[3:0]

b3, b2, b1, b0

1011

Controls RLC DAC driving VRLC pin, to define single-ended signal-reference voltage

or reset-level clamp voltage. F(hex) is VDD, 0(hex) is 0V, B(hex) (default) is 11/15

∗

AVDD (= 3.67V typically).

RLCEXT

Powers down the RLC DAC, tri-stating its output, allowing VRLC to be externally driven.

RLCEXT

RLC DAC drives VRLC pin

RLC DAC Hi-Z

PGAFS[1:0]

b6, b5

Configures the ADC input to accept the following video signal types:

PGAFS[1] PGAFS[0]

Bipolar video

Negative-going video

Positive-going video

Revision Number

Address

000111

REV[7:0]

b7, …..b0

Read-only register, allows the user to determine the revision level of the device.

ASCII 7-bit code, e.g. 43(hex) = C

DAC Values

Address

1000xy

DAC[7:0]

b7, …..b0

1000

0000

The offset-setting data for the Red, Green and Blue offset DACs. 00(hex) gives

-200mV offset referred to signal input, FF(hex) gives +200mV, 80(hex) (default) gives

approximately zero offset.

PGA Gains

Address

1010xy

PGA[5:0]

b5, ….. b0

000000

The gain setting data for the Red, Green, and Blue programmable gain amplifiers.

00(hex) gives min gain, 3F(hex) gives max gain.

Table 8 Control Register Bit Descriptions

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