WM8148 datasheet(20/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the processing of the video and reset level signals through the

WM8148.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If MODE[0] = 0, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from

the input video.

=VIN - VRESET

Eqn. 1

If MODE[0] = 1, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

=VIN - VVRLC

Eqn. 2

If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC.

If RLCEXT = 0, VVRLC is the output from the internal RLC DAC.

VVRLC

AVDD

∗ RLCV[3:0] / 15

Eqn. 3

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal V1 is added to the Offset DAC output.

V1 + 200mV

∗ (DAC[7:0]-127.5) / 127.5

Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain,

∗ 52/(70- PGA[5:0])

Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 12-bit unsigned number, with input range configured by

PGAFS[1:0].

D1[11:0] = INT{ (V3 /VFS)

∗ 4095} + 2047

PGAFS[1:0] = 00 or 01

Eqn. 6

D1[11:0] = INT{ (V3 /VFS)

∗ 4095}

PGAFS[1:0] = 11

Eqn. 7

D1[11:0] = INT{ (V3 /VFS)

∗ 4095} + 4095

PGAFS[1:0] = 10

Eqn. 8

where the ADC full-scale range, VFS, = 3V.

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

D2[11:0] = D1[11:0]

(INVOP = 0)

Eqn. 9

D2[11:0] = 4095 – D1[11:0]

(INVOP = 1)

Eqn. 10

OUTPUT DATA FORMAT

MULTIPLEXED AND NON-MULTIPLEXED OUTPUT FORMAT

Data is output from the device, by default, as a 12-bit wide word on OP[11:0]. The output changes on

every Nth negative-going edge of MCLK where N = 2, 4, or 6 according to the video sampling mode.

This is shown as byte C in Figure 21.

If control bit MUXOP is set high, data is output in a 2 x 8-bit word format, with data changing every

Nth negative-going edge of MCLK, where N = 1, 2, or 3 according to video sampling mode. This is

shown as bytes A and B in Figure 21. Data is presented on pins OP[11:4] at twice the output pixel

rate. Bits CC[1] and CC[0] are used to indicate which channel the ADC input was taken from. Table 3

shows the channels corresponding to the CC[1:0] bit values. Bits TVIOL and OVRNG of byte B are

Error Flags, these are described below.

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