TMS320DM365 datasheet(59/211 Pages) TI

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Pre-DIV

(Programmable)

PLL

PLLEN

PLLM

(Programmable)

Post-DIV

(Programmable)

OSCIN

PLLDIV1*

SYSCLK1 (USBReferenceClock)

PLLDIV2*

SYSCLK2(ARM926EJ-S,HDVICP

BlockClock)

PLLDIV3*

SYSCLK3(MJCP andHDVICP

CoprocessorsBusInterfaceClock)

PLLDIV4*

SYSCLK4(ConfigBus,PeripheralSystem

Interfaces,EDMA)

PLLDIV5*

SYSCLK5(VPSS)

PLLDIV6*

SYSCLK6(VENCClock)

PLLDIV7*

SYSCLK7(DDR2xClock)

PLLDIV8*

SYSCLK8(MMC/SD0Clock)

PLLDIV9*

SYSCLK9(CLKOUT2)

OSCDIV1*

BPDIV*

OBSCLK(CLKOUT0)

SYSCLKBP (

* – Programmable

USBReferenceClock)

TMS320DM365

www.ti.com

SPRS457C – MARCH 2009 – REVISED APRIL 2010

Figure 3-3. PLLC1 Configuration

3.3.4

PLLC2

PLLC2 provides the USB reference clock , ARM926EJ-S, DDR 2x clock, Voice Codec clock and VENC

27MHz, 74.25MHz clock. The PLLC2 functionality can be programmed via the PLLC2 registers. The

following list, Table 3-3, and Figure 3-4 describe the customization of PLLC2.

The PLLC2 customization includes the following features:

•

PLLC2 provides DDR PHY, USB reference clock , ARM926EJ-S clock, VENC 27MHz, 74.25Hz clock

and Voice codec clock

•

Software configurable

•

Accepts clock input or internal oscillator input (the same input as PLLC1)

•

PLL pre-divider value is programmable

•

PLL multiplier value is programmable

•

PLL post-divider value is programmable

•

Only SYSCLK [5:1] are used

Table 3-3. PLLC2 Output Clocks

PLLC2SYSCLKy

Used by

PLLDIV Divider

PLLC2SYSCLK1

USB reference clock(1)

Programmable

PLLC2SYSCLK2

ARM926EJ-S, HDVICP block clock (1)

Programmable

PLLC2SYSCLK3

DDR 2x clock (1)

Programmable

PLLC2SYSCLK4

Voice Codec clock

Programmable

PLLC2SYSCLK5

VENC clock (1)

Programmable

PLLC2OBSCLK

CLKOUT1

Programmable

(1)

These clock outputs are multiplexed with other clocks.

Device Configurations

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