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TMS320DM365 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM365 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 211 page  TMS320DM365 www.ti.com SPRS457C – MARCH 2009 – REVISED APRIL 2010 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 MAC • Highlights – ARM® Javelle® Technology – High-Performance Digital Media System-on-Chip (DMSoC) – Embedded ICE-RT Logic for Real-Time Debug – Up to 300-MHz ARM926EJ-S Clock Rate • ARM9 Memory Architecture – Two Video Image Co-processors (HDVICP, MJCP) Engines – 16K-Byte Instruction Cache – Supports a Range of Encode, Decode, and – 8K-Byte Data Cache Video Quality Operations – 32K-Byte RAM – Video Processing Subsystem – 16K-Byte ROM • HW Face Detect Engine – Little Endian • Resize Engine from 1/16x to 8x • Two Video Image Co-processors • 16-Bit Parallel AFE (Analog Front-End) (HDVICP, MJCP) Engines Interface Up to 120 MHz – Support a Range of Encode and Decode • 4:2:2 (8-/16-bit) Interface Operations • 3 DACs for HD Analog Video Output – H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1 • Hardware On-Screen Display (OSD) • Video Processing Subsystem – Capable of 720p 30fps H.264 video processing – Front End Provides: – Peripherals include EMAC, USB 2.0 OTG, • HW Face Detect Engine DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Hardware IPIPE for Real-Time Image MMC/SD/SDIO, Key Scan Processing – 8 Different Boot Modes and Configurable – Resize Engine Power-Saving Modes – Resize Images From 1/16x to 8x – Pin-to-pin and software compatible with – Separate Horizontal/Vertical DM368 Control – Extended temperature (-40ºC – 85ºC) – Two Simultaneous Output Paths available for 300-Mhz device • IPIPE Interface (IPIPEIF) – 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core • Image Sensor Interface (ISIF) and CMOS – Debug Interface Support Imager Interface – 338-Pin Ball Grid Array at 65nm Process • 16-Bit Parallel AFE (Analog Front End) Technology Interface Up to 120 MHz • High-Performance Digital Media • Glueless Interface to Common Video System-on-Chip (DMSoC) Decoders – 216-, 270-, 300-MHz ARM926EJ-S Clock Rate • BT.601/BT.656/BT.1120 Digital YCbCr – Fully Software-Compatible With ARM9™ 4:2:2 (8-/16-Bit) Interface – Extended temperature available for 300-Mhz • Histogram Module device • Lens distortion correction module (LDC) • ARM926EJ-S™ Core • Hardware 3A statistics collection module – Support for 32-Bit and 16-Bit (H3A) (Thumb® Mode) Instruction Sets – Back End Provides: – DSP Instruction Extensions and Single Cycle 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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