TMS320DM365 datasheet(63/211 Pages) TI

63 / 211 page

arm_clock

arm_mreset

arm_power

AINTC

ARM

module_power

module_mreset

MODx

module_clock

Alwayson

domain

Interrupt

PSC

clks

PLLC

Emulation

RESETN

VDD

DMSoC

TMS320DM365

www.ti.com

SPRS457C – MARCH 2009 – REVISED APRIL 2010

3.3.7

Peripheral Clocking Considerations

The device supports several peripherals with special clocking considerations (VPBE, USB, Key Scan,

ADC, Voice Codec, MJCP, HDVICP, AUXCLK, DDR2 EMIF). For more detail on these special

considerations, see the Peripheral Clocking Considerations section of theTMS320DM36x DMSoC ARM

Subsystem Reference Guide (literature number SPRUFG5).

3.4

Power and Sleep Controller (PSC)

In the device system, the Power and Sleep Controller (PSC) is responsible for managing transitions of

system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of

the operations of the PSC are transparent to software, such as power-on-reset operations. However, the

PSC provides you with an interface to control several important clock and reset operations.

The PSC includes the following features:

•

Manages chip power-on/off, clock on/off, and resets

•

Provides a software interface to:

–

Control module clock ON/OFF

–

Control module resets

•

Supports IcePick emulation features: power, clock, and reset

Figure 3-5. Power and Sleep Controller (PSC)

For more information on the PSC, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide

(literature number SPRUFG5).

Device Configurations

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