TMS320DM365 datasheet(12/211 Pages) TI

12 / 211 page

TMS320DM365

SPRS457C – MARCH 2009 – REVISED APRIL 2010

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2.3.10 Peripherals

The ARM has access to all of the peripherals on the device.

2.3.11 ARM Interrupt Controller (AINTC)

The device ARM Interrupt Controller (AINTC) has the following features:

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Supports up to 64 interrupt channels (16 external channels)

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Interrupt mask for each channel

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Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request

(IRQ) type of interrupt.

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Hardware prioritization of simultaneous interrupts

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Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ)

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Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time

The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference

Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is

mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The

INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize

the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding

highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can

read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a

software dispatcher to determine the asserted interrupt.

2.4

System Control Module

The system control module is a system-level module containing status and top-level control logic required

by the device. The system control module consists of a miscellaneous set of status and control registers,

accessible by the ARM and supporting all of the following system features and operations:

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Device identification

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Device configuration

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Pin multiplexing control

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Device boot configuration status

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ARM interrupt and EDMA event multiplexing control

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Special peripheral status and control

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Timer64

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USB PHY control

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VPSS clock and video DAC control and status

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DDR VTP control

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Clockout circuitry

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GIO de-bounce control

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Power management

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Deep sleep

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Bandwidth Management

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Bus master DMA priority control

For more information on the System Control Module refer to Section 3, Device Configurations and the

TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).

Device Overview

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