TMS320DM365 datasheet(13/211 Pages) TI

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TMS320DM365

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SPRS457C – MARCH 2009 – REVISED APRIL 2010

2.5

Power Management

The device is designed for minimal power consumption. There are two components to power

consumption: active power and leakage power. Active power is the power consumed to perform work and

scales with clock frequency and the amount of computations being performed. Active power can be

reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to

complete the required operation in the required time-line or to run at a clock setting until the work is

complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be

performed. Leakage power is due to static current leakage and occurs regardless of the clock rate.

Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating

junction temperatures. Leakage power can only be avoided by removing power completely from a device

or subsystem. The device includes several power management modes which are briefly described in

Table 2-2. See the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number

SPRUFG5) for more information on power management.

Table 2-2. Power Management Conditions

GIO,

SPI,

POWER MGMT.

OTHER

DDR

CORE

OSC.

PLL

ARM926

UART,

PWM,

APPLICATION

PRTCSS

PERIPH.

CLOCK/

DESCRIPTION

POWER

CNTRLR.

CLOCK

I2C

TIMER

SCENARIO

CLOCKS

MODE

CLOCKS

This condition

consumes the lowest

PRTCSS

Active

Off

possible power, except

for the PRTCSS.

This mode consumes

the second lowest

Bypass

Suspend /

possible power, except

Mode

Deep Sleep Mode(1)

Active

Off

"Self-

for PRTCSS and core

(not

Refresh"

power, where only the

Active)

deep sleep circuit is on

in this mode.

This condition keeps

the minimum possible

modules powered-on

Suspend /

in order to wake up the

Bypass

Standby

Active

Off

"Self-

device. Clocks are

Mode

Refresh"

suspended except for

GIO (interrupts),

UART, and I2C (in

slave mode).

Most clocks are

suspended, except for

ARM, GIO, UART,

SPI, I2C, PWM, and

Suspend /

Low-power

Bypass

timers. Since ARM will

Active

On / Off

"Self-

(PLL Bypass Mode)

Mode

not have access to

Refresh"

DDR, its internal

Cache will be either

frozen or not

accessed.

The device, including

Nominal

system PLLs, are on.

System Running

Active

PLL Mode

On / Off

Clock /

This condition

(PLL Mode)

Operation

conserves the least

amount of power.

(1)

For more details, see TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5)

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