LPC1759 datasheet(22/64 Pages) NXP

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LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

22 of 64

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

7.16 UARTs

The LPC1759/58/56/54/52/51 each contain four UARTs. In addition to standard transmit

and receive data lines, UART1 also provides a full modem control handshake interface

and support for RS-485/9-bit mode allowing both software address detection and

automatic address detection using 9-bit mode.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.16.1 Features

• Maximum UART data bit rate of 6.25 MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

• Support for RS-485/9-bit/EIA-485 mode (UART1).

• UART3 includes an IrDA mode to support infrared communication.

• All UARTs have DMA support.

7.17 SPI serial I/O controller

The LPC1759/58/56/54/52/51 contain one SPI controller. SPI is a full duplex serial

interface designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the

slave, and the slave always sends 8 bits to 16 bits of data to the master.

7.17.1 Features

• Maximum SPI data bit rate of 12.5 Mbit/s

• Compliant with SPI specification

• Synchronous, serial, full duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

7.18 SSP serial I/O controller

The LPC1759/58/56/54/52/51 contain two SSP controllers. The SSP controller is capable

of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters

and slaves on the bus. Only a single master and a single slave can communicate on the

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