LPC1759 datasheet(30/64 Pages) NXP

30 / 64 page

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

30 of 64

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

7.29.2 Main PLL (PLL0)

The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input

frequency is multiplied up to a high frequency, then divided down to provide the actual

clock used by the CPU and/or the USB block.

The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a

value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range

of output frequencies from the same input frequency.

Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the

range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a

phase-frequency detector to compare the divided CCO output to the multiplier input. The

error value is used to adjust the CCO frequency.

The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL0 is enabled by software only. The program must configure and activate the

PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source.

7.29.3 USB PLL (PLL1)

The LPC1759/58/56/54/52/51 contain a second, dedicated USB PLL1 to provide clocking

for the USB interface.

The PLL1 receives its clock input from the main oscillator only and provides a fixed

48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the

PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main

PLL0.

The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The

input frequency is multiplied up the range of 48 MHz for the USB clock using a Current

Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle.

7.29.4 Wake-up timer

The LPC1759/58/56/54/52/51 begin operation at power-up and when awakened from

Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip

operation to resume quickly. If the main oscillator or the PLL is needed by the application,

software will need to enable these features and wait for them to stabilize before they are

used as a clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufficient amplitude to drive the clock logic. The amount of time depends on many factors,

including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its

LPC1759 Datasheet(PDF) 30 Page - NXP Semiconductors

LPC1759 Datasheet(HTML) 30 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL