LPC1759 datasheet(14/64 Pages) NXP

14 / 64 page

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

14 of 64

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to 8 regions each of which can be

divided into 8 subregions. Accesses to memory locations that are not defined in the MPU

regions, or not permitted by the region setting, will cause the Memory Management Fault

exception to take place.

7.6 Memory map

The LPC1759/58/56/54/52/51 incorporate several distinct memory regions, shown in the

following figures. Figure 3 shows the overall map of the entire address space from the

user program viewpoint following reset. The interrupt vector area supports address

remapping.

The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

LPC1759 Datasheet(PDF) 14 Page - NXP Semiconductors