LMP8358 datasheet(20/32 Pages) NSC

20 / 32 page

Table 3. Function of Digital IO Pins, Serial Mode

Pin Name

Description

SDO

Serial Data Out

SDI

Serial Data In

SCK

Serial Clock

CSB

Chip Select

VLSER

Negative Logic level

VHSER

Positive Logic Level

Table 4. LMP8358 Register Description, Serial Mode

Bit No

Name

Description

Gain setting (LSB)

Gain setting

Gain setting (MSB)

COMP0

Frequency compensation setting (LSB)

COMP1

Frequency compensation setting

COMP2

Frequency compensation setting (MSB)

MUX0

Input multiplexer selection (LSB)

MUX1

Input multiplexer selection (MSB)

POL

Input polarity switch

SHDN

Shutdown Enable

FILT

Enable filtering using external cap

Bit No

Name

Description

Fault detection pin selection

CUR0

Fault detection current setting (LSB)

CUR1

Fault detection current setting

CUR2

Fault detection current setting (MSB)

N/A

Unused, set to 0

Serial Control Interface Operation

The LMP8358 gain, bandwidth compensation, shutdown, in-

put options, and fault detection are controlled by an on board

programmable register. Data to be written into the control

face. The serial interface employs an 16-bit double-buffered

loaded through the serial data input, SDI. Data passing

through the shift register is output through the serial data out-

put, SDO. The serial clock, SCK controls the serial loading

process. All sixteen data bits are required to correctly program

the amplifier. The falling edge of CSB enables the shift reg-

ister to receive data. The SCK signal must be high during the

falling and rising edge of CSB. Each data bit is clocked into

the shift register on the rising edge of SCK. Data is transferred

from the shift register to the holding register on the rising edge

of CSB. Operation is shown in the SPI Timing Diagram.

The serial control pins can be connected in one of two ways

when two or more LMP8358s are used in an application.

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