The following two examples show how the registers are writ-

ten in the Daisy Chain Configuration.

Tabel 5. If all three LMP8358s need a gain of 100 with a compensation level of 010. (0000 0000 0001 0011)

Register of LMP8358 #1 Register of LMP8358 #2 Register of LMP8358 #3 Notes

Power on

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

Default power on state

After first two bytes are

sent

0000 0000 0001 0011

0000 0000 0000 0000

0000 0000 0000 0000

The data in the register of

LMP8358 #1 is shifted

into the register of

LMP8358 #2, the data in

the register of LMP8358

#2 is shifted into the

register of LMP8358 #3.

After second two bytes

are sent

0000 0000 0001 0011

0000 0000 0001 0011

0000 0000 0000 0000

After third two bytes

are sent

0000 0000 0001 0011

0000 0000 0001 0011

0000 0000 0001 0011

Table 6. If LMP8358 #1 needs a gain of 20 (0000 0000 0000 0001), LMP8358 #2 needs a gain of 1000 with a compensation

level of 011 (0000 0000 0001 1110), and LMP8358 #3 needs a gain of 100 with a compenstation level of 010 (0000 0000 0001

0011).

Register of LMP8358 #1 Register of LMP8358 #2 Register of LMP8358 #3 Notes

Power on

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

Default power on state

After first two bytes are

sent

0000 0000 0001 0011

0000 0000 0000 0000

0000 0000 0000 0000

The data in the register of

LMP8358 #1 is shifted

into the register of

LMP8358 #2, the data in

the register of LMP8358

#2 is shifted into the

register of LMP8358 #3

After second two bytes

are sent

0000 0000 0001 1110

0000 0000 0001 0011

0000 0000 0000 0000

After third two bytes

are sent

0000 0000 0000 0001

0000 0000 0001 1110

0000 0000 0001 0011

LMP8358 SETTINGS

Gain (Serial, Parallel)

When the LMP8358 is in Parallel Mode the gain can be set

by applying a high or low level to pins 12 (G2), 13 (G1), and

14 (G0), as shown in Table 2. Pin Levels for Setting Gain,

Parallel Mode. The Frequency Compensation bits are auto-

matically set as shown in Table 2. Pin Levels for Setting Gain,

Parallel Mode to optimize the bandwidth. In Serial Mode the

gain is determined by setting G[2:0] as shown in Table 7. Gain

Setting (Register bits 2:0) and the bandwidth can be changed

using the Frequency Compensation bits in the register.

Table 7. Gain Setting (Register bits 2:0)

G2

G1

G0

Gain Setting

0

0

0

10x (power-up default)

0

0

1

20x

0

1

0

50x

0

1

1

100x

1

0

0

200x

1

0

1

500x

1

1

0

1000x

1

1

1

User Defined

When G[2:0] = 000b to 110b switch S1 is closed and switch

S2 is open as shown in the Block Diagram.

When G[2:0] = 111b in either serial or parallel mode switch

S1 is open and S2 is closed and the LMP8358 gain is set by

external resistors as shown in Figure 6. The gain is:

GAIN = 1 + (Z1/Z2)

When the gain is set by external resistors and COMP[2:0] =

1xxb, a capacitor can be used to implement a noise reduction

low pass filter. See the Filter and External Filter Capacitor

(Serial) section. R1and C

and FB pins. R2 is placed between the FB and REFS pins.

300454a6

FIGURE 6. External Gain Set Resistors and Filter

Capacitor

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