LT3579 datasheet(7/40 Pages) LINER

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LT3579/LT3579-1

35791f

PIN FUNCTIONS

GATE (Pin 1/Pin 3): PMOS Gate Drive Pin. The GATE pin

is a pull-down current source, and can be used to drive

the gate of an external PMOS transistor for output short

circuit protection or output disconnect. The GATE pin

current increases linearly with the SS pin’s voltage, with

a maximum pull-down current of 933μA at SS voltages

exceeding 500mV. Note that if the SS voltage is greater

than 500mV, and the GATE pin voltage is less than 2V, the

GATE pin looks like a 2kΩ impedance to ground. See the

Appendix for more information.

FAULT (Pin 2/Pin 4): Fault Indication Pin. This active

low, bidirectional pin can either be pulled low (below

750mV) by an external source, or internally by the chip

to indicate a fault. When pulled low, this pin causes the

power switches to turn off, the GATE pin to become high

impedance, the CLKOUT pin to become disabled, and the

SS pin to go through a charge/discharge sequence. The

end/absence of a fault is indicated when the voltage on this

pin exceeds 1V. A pull-up resistor or some other form of

pull-up network needs to exist on this pin to pull it above

1V in the absence of a fault.

VIN (Pin 3/Pin 5): Input Supply Pin. Must be locally

bypassed.

SW1 (Pins 4 - 7/Pins 6 - 10): Master Switch Pin. This is the

collector of the internal master NPN power switch. SW1

is designed to handle a peak collector current of 3.4A

(minimum). Minimize the metal trace area connected to

this pin to minimize EMI.

GND (Pins 8, 9, Exposed Pad Pin 21/Exposed Pad Pin 21):

Ground. Must be soldered directly to local ground

plane.

SW2 (Pins 10-13/Pins 11-15): Slave Switch Pin. This is

the collector of the internal slave NPN power switch. SW2

is designed to handle a peak collector current of 2.6A

(minimum). Minimize the metal trace area connected to

this pin to minimize EMI.

CLKOUT (Pin 14/Pin 16): Clock Output Pin. Use this pin to

synchronize one or more other ICs to the LT3579. This pin

oscillates at the same frequency as the internal oscillator of

the part or as the SYNC pin. CLKOUT may also be used as

a temperature monitor since the CLKOUT pin’s duty cycle

varies linearly with the part’s junction temperature. The

CLKOUT pin signal of the LT3579-1 is 180° out of phase

with the internal oscillator or SYNC pin, and the duty cycle

is ﬁxed at ~50%. The LT3579-1 is useful for multiphase

switching regulators.

SHDN (Pin 15/Pin 17): Shutdown Pin. In conjunction

with the UVLO (undervoltage lockout) circuit, this pin is

used to enable/disable the chip and restart the soft-start

sequence. Drive below 0.3V to disable the chip with very

low quiescent current. Drive above 1.33V (typical) to

activate the chip and restart the soft-start sequence. Do

not ﬂoat this pin.

RT (Pin 16/Pin 18): Timing Resistor Pin. Adjusts the

LT3579’s switching frequency. Place a resistor from this

pin to ground to set the frequency to a ﬁxed free running

level. Do not ﬂoat this pin.

SYNC (Pin 17/Pin 20): To synchronize the switching

frequency to an outside clock, simply drive this pin with

a clock. The high voltage level of the clock must exceed

1.3V, and the low level must be less than 0.4V. Drive this

pin to less than 0.4V to revert to the internal free running

clock. See the Applications Information section for more

information.

SS (Pin 18/Pin 19): Soft-Start Pin. Place a soft-start

capacitor here. Upon start-up, the SS pin will be charged

by a (nominally) 250kΩ resistor to ~2.1V. During a fault,

the SS pin will be slowly charged up and discharged as

part of a timeout sequence.

VC (Pin 19/Pin 2): Error Ampliﬁer Output Pin. Tie external

compensation network to this pin.

FB (Pin 20/Pin 1): Positive and Negative Feedback Pin.

For a Boost or Inverting Converter, tie a resistor from the

FB pin to VOUT according to the following equations:

µA

Boost or SEPIC Con

OUT

⎛

⎝

⎜

⎞

⎠

⎟

–.

;

1 215

83 3

vverter

VmV

µA

Inverting

OUT

⎛

⎝

⎜

⎞

⎠

⎟

;

83 3

Converter

(QFN/TSSOP)

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