AD5308 datasheet(17/24 Pages) AD

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AD5308/AD5318/AD5328

Rev. D | Page 17 of 24

Control Functions

In the case of a control function, the MSB (Bit 15) is a 1. This is

followed by two control bits, which determine the mode. There

are four different control modes: reference and gain mode, LDAC

mode, power-down mode, and reset mode. The write sequences

for these modes are shown in Table 7.

Reference and Gain Mode

This mode determines whether the reference for each group of

DACs is buffered, unbuffered, or from VDD. It also determines

the gain of the output amplifier. To set up the reference of both

groups, set the control bits to (00), set the GAIN bits, the BUF

bits, and the VDD bits.

BUF

This controls whether the reference of a group of DACs is

buffered or unbuffered. The reference of the first group of DACs

(A, B, C, and D) is controlled by setting Bit 2, and the second

group of DACs (E, F, G, and H) is controlled by setting Bit 3.

0: unbuffered reference.

1: buffered reference.

GAIN

The gain of the DACs is controlled by setting Bit 4 for the first

group of DACs (A, B, C, and D) and Bit 5 for the second group

of DACs (E, F, G, and H).

0: output range of 0 V to VREF.

1: output range of 0 V to 2 VREF.

Table 7. Control Words for the AD53x8

D/C

Control Bits

Mode

GAIN Bits

BUF Bits

VDD Bits

Gain of output amplifier and

E...H

A...D

E...H

A...D

E...H

A...D

reference selection

LDAC Bits

1/0

LDAC

Channels

Power-down

Reset

1/0

Reset

BIT 0

(LSB)

BIT 15

(MSB)

DATA BITS

D/C

Figure 32. AD5308 Input Shift Register Contents

DATA BITS

BIT 0

(LSB)

BIT 15

(MSB)

D/C

Figure 33. AD5318 Input Shift Register Contents

DATA BITS

BIT 0

(LSB)

BIT 15

(MSB)

D10

D11

D/C

Figure 34. AD5328 Input Shift Register Contents

VDD

These bits are set when VDD is to be used as a reference. The

first group of DACs (A, B, C, and D) can be set up to use VDD by

setting Bit 0, and the second group of DACs (E, F, G, and H) by

setting Bit 1. The VDD bits have priority over the BUF bits.

When VDD is used as the reference, it is always unbuffered and

has an output range of 0 V to VREF regardless of the state of the

GAIN and BUF bits.

LDAC Mode

LDAC mode controls LDAC, which determines when data is

transferred from the input registers to the DAC registers. There

are three options when updating the DAC registers, as shown in

Table 8.

Table 8. LDAC Mode

Bit 15

Bit 14

Bit 13

Bits 12:2

Bit 1

Bit 0

Description

x ... x

LDAC low

x ... x

LDAC high

x ... x

LDAC single

update

x ... x

Reserved

LDAC Low (00): This option sets LDAC permanently low,

allowing the DAC registers to be updated continuously.

LDAC High (01): This option sets LDAC permanently high.

The DAC registers are latched and the input registers can

change without affecting the contents of the DAC registers.

This is the default option for this mode.

LDAC Single Update (10): This option causes a single pulse on

LDAC, updating the DAC registers once.

Reserved (11): reserved.

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