TPS54521

www.ti.com

SLVS981 – JUNE 2010

Thermal Performance

Figure 56. Thermal Signature of Example Circuit Operating at

Table 2. Bill of Materials

COUNT

RefDes

Value

Description

Size

Part Number

MFR

1

C2

10µF

Capacitor, Ceramic, 25V, X5R, 20%

1210

Std

Std

1

C3

4.7µF

Capacitor, Ceramic, 25V, X5R, 10%

0805

Std

Std

1

C4

5600pF

Capacitor, Ceramic, 50V, X7R, 10%

0603

Std

Std

1

C5

0.1µF

Capacitor, Ceramic, 16V, X7R, 10%

0603

Std

Std

1

C6

560pF

Capacitor, Ceramic, 50V, C0G, 5%

0603

Std

Std

1

C7

0.01µF

Capacitor, Ceramic, 10V, X7R, 10%

0603

Std

Std

1

C8

10µF

Capacitor, Ceramic, 10V, X5R, 10%

0805

Std

Std

Capacitor, Alum Electrolytic 6.3 V, 125mOhm

EKZE6R3ELL33

1

C9

330µF

6.30 mm Dia

Chemi-con

ESR, ±20%

1MF11D

1

C11

100pF

Capacitor, Ceramic, 50V, C0G, 5%

0603

Std

Std

1

L1

3.3µH

Inductor, 12mOhm DCR, 7.5A, ± 20%

0.300 Dia. inch

DR0608-332L

Coilcraft

1

R1

511K

Resistor, Chip, 1/16W, 1%

0603

Std

Std

2

R2, R3

100K

Resistor, Chip, 1/16W, 1%

0603

Std

Std

1

R4

38.3K

Resistor, Chip, 1/16W, 1%

0603

Std

Std

1

R7

51.1

Resistor, Chip, 1/16W, 1%

0603

Std

Std

1

R8

31.6K

Resistor, Chip, 1/16W, 1%

0603

Std

Std

1

R9

10.0K

Resistor, Chip, 1/16W, 1%

0603

Std

Std

IC, 17V Input, 5A Output, Sync. Step Down

1

U1

TPS54521RHL

QFN14

TPS54521RHL

TI

Switcher With Integrated FET

PCB Layout Guidelines

Layout is a critical portion of good power supply design. See Figure 57 for a PCB layout example. The top layer

contains the main power traces for VIN, VOUT, and the PH node. Also on the top layer are connections for the

remaining pins of the TPS54521 and a large top side area filled with ground. The top layer ground area should

be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor

and directly under the TPS54521 device to provide a thermal path from the exposed thermal pad land to ground.

The GND pin should be tied directly to the exposed thermal pad under the IC. For operation at full rated load, the

top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There

are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance

or parasitic capacitance to generate noise or degrade the power supply's performance. To help eliminate these

problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or

X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the

PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic

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