TMS320DM6441 datasheet(8/232 Pages) TI

8 / 232 page

TMS320DM6441

Digital Media System-on-Chip

SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008

www.ti.com

Table 2-1. TMS320DM6441 Revision History (continued)

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 7.13.2.3

(1), Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With

VPBE Electrical

Respect to PCLK and VPBECLK:

Data/Timing

•

Split the MIN/MAX values for 1.05 V and 1.2 V

•

Updated/changed the 1.05 V MAX values of NO. 11, 13, 29, and 31 from "13.3" to "16" ns

Table 7-63, Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data

Output With Respect to VCLK:

•

Split the MIN/MAX values for 1.05 V and 1.2 V

•

Added MODE column

•

Updated/changed the following Parameters:

–

Parameter NO. 23 td(VCLK-VCTLV), split into VCLK positive/negative; regardless of MODE

–

Parameter NO. 24 td(VCLKL-VCTLIV), split into VCLK positive/negative; regardless of MODE

–

Parameter NO. 25 td(VCLK-VDATAV), split into VCLK positive/negative; regardless of MODE

–

Parameter NO. 26 td(VCLKL-VDATAIV), split into VCLK positive/negative; separated by MODE: RGB or YCC

•

Added associated MODE footnote

Section 7.13.2.4

Updated/changedFigure 7-54, Typical Output Circuit for NTSC/PAL Video From DACs

DAC Electrical

Data/Timing

(was Subsection 7.25)

Deleted the "Video Processing Sub-System (VPSS) Overview" subsection (was Subsection 7.25)

Video Processing

Sub-System (VPSS)

Overview

(1)

PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising

edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.

Revision History

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