TMS320DM6441 datasheet(83/232 Pages) TI

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System Interconnect

TMS320DM6441

Digital Media System-on-Chip

www.ti.com

SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008

On the DM6441 device, the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers,

and the system peripherals are interconnected through a switch fabric architecture (shown in Figure 5-1).

The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The

SCRs establish low-latency connectivity between master peripherals and slave peripherals. Additionally,

the SCRs provide priority-based arbitration and facilitate concurrent data movement between master and

slave peripherals. Through SCR, the ARM subsystem can send data to the DDR2 Memory Controller

without affecting a data transfer between the EMAC and L2 memory. Bridges are mainly used to perform

bus-width conversion as well as bus operating frequency conversion. For example, in Figure 5-1, Bridge 8

performs a frequency conversion between a bus operating at DSP/6 clock rate and a bus operating at

DSP/3 clock rate. Furthermore, Bridge 3 performs a bus-width conversion between a 64-bit bus and a

32-bit bus.

The C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the various system

peripherals can be classified into two categories: master peripherals and slave peripherals. Master

peripherals are typically capable of initiating read and write transfers in the system and do not rely on the

EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include the

C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, CF/ATA, VLYNQ, EMAC, USB,

and VPSS. Not all master peripherals may connect to all slave peripherals. The supported connections

are designated by an X in Table 5-1.

Table 5-1. System Connection Matrix

SLAVE

MASTER

C64x+

ARM

DDR2 MEMORY CONTROLLER

SCR3(1)

C64x+

ARM

VPSS

CF/ATA

VLYNQ

EMAC

USB

EDMA3TC0

EDMA3TC1

HPI

X(2)

(1)

The C64x+ megamodule has access to only the following peripherals connected to SCR3: EDMA3, ASP, and Timers. All other

peripherals/modules that support a connection to SCR3 have access to all peripherals/modules connected to SCR3.

(2)

HPI's access to SCR3 is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and HPI configuration registers.

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System Interconnect

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