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TMS320DM6441 Datasheet(PDF) 22 Page - Texas Instruments |
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TMS320DM6441 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 232 page  3.6 Pin Assignments 3.6.1 Pin Map (Bottom View) W V U T R P N M L K 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 DDR_D[1] DVDDR2 EM_A[4]/ GPIO27 CLK_OUT0/ GPIO48 MXI/CLKIN EM_A[5]/ GPIO26 MXVSS PLLVDD18 RSV24 EM_A[6]/ GPIO25 EM_A[8]/ GPIO23 EM_A[7]/ GPIO24 EM_A[13]/ GPIO18 EM_A[10]/ GPIO21 EM_A[15]/ GPIO16/ VLYNQ_TXD3 EM_A[11]/ GPIO20 EM_A[17]/ GPIO14/ VLYNQ_TXD2 EM_A[19]/ GPIO12/ VLYNQ_TXD1 EM_A[20]/ GPIO11/ VLYNQ_RXD0 EM_CS4/ GPIO9/ VLYNQ_ SCRUN DDR_ DQM[0] DDR_D[0] EM_A[21]/ GPIO10/ VLYNQ_TXD0 EM_A[14]/ GPIO17/ VLYNQ_RXD3 EM_A[9]/ GPIO22 MXVDD RESET VSS RSV3 VSS CVDD DVDDR2 DVDDR2 VSS VSS DDR_A[11] DDR_A[12] DDR_CLK0 DDR_CLK0 DDR_D[14] DVDDR2 VSS VSS DDR_D[5] DDR_D[6] DDR_D[9] DVDD18 EM_A[16]/ GPIO15/ VLYNQ_RXD2 DVDDR2 DDR_BS[2] CVDD DDR_D[11] DDR_D[15] DDR_CKE DDR_A[8] VSS DVDDR2 VSS VSS DVDDR2 DDR_ DQM[1] DDR_CAS DDR_WE DDR_VDDDLL CVDDDSP CVDD DDR_DQS[1] DDR_RAS DDR_A[10] CVDD CVDD DDR_D[2] DDR_D[3] DDR_D[8] DDR_D[13] DDR_BS[1] DDR_D[4] DDR_D[12] VSS EM_A[3]/ GPIO28 DVDD18 CVDD DVDD18 RSV7 MXO VSS DVDD18 VSS EM_A[18]/ GPIO13/ VLYNQ_RXD1 VSS EM_A[12]/ GPIO19 VSS DDR_CS CVDDDSP DDR_DQS[0] DDR_D[10] DDR_BS[0] EM_CS5/ GPIO8/ VLYNQ_ CLOCK RSV6 DDR_D[7] W V U T R P N M L K TMS320DM6441 Digital Media System-on-Chip SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008 www.ti.com Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 4.5.2, Multiplexed Pin Configurations, of this document. Figure 3-2 through Figure 3-5 show the bottom view of the package pin assignments in four quadrants (A, B, C, and D). Figure 3-2. Pin Map [Quadrant A] Device Overview 22 Submit Documentation Feedback |
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