Contents

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

1

Introduction

......................................................................................................................... 7

1.1

Features

....................................................................................................................... 7

1.2

Description

.................................................................................................................... 7

1.3

Ordering Information

........................................................................................................ 7

1.4

Device Information

........................................................................................................... 8

1.5

Revision History

............................................................................................................ 11

2

Functional Description

........................................................................................................ 12

2.1

MCU Memory Map

......................................................................................................... 12

2.2

Miscellaneous Registers

.................................................................................................. 13

2.2.1

TUSB3210 Boot Operation

..................................................................................... 13

2.2.2

MCNFG: MCU Configuration Register

........................................................................ 13

2.2.3

PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

....................................................... 14

2.2.4

INTCFG: Interrupt Configuration

.............................................................................. 14

2.2.5

WDCSR: Watchdog Timer, Control, and Status Register

.................................................. 14

2.2.6

PCON: Power Control Register (at SFR 87h)

............................................................... 15

2.3

Buffers + I/O RAM Map

.................................................................................................... 16

2.4

Endpoint Descriptor Block (EDB-1 to EDB-3)

.......................................................................... 18

2.4.1

OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)

................................................... 19

2.4.2

OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3)

..................................... 20

2.4.3

OEPBCTX_n: Output Endpoint X-Byte Count (n = 1 to 3)

................................................. 20

2.4.4

OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3)

..................................... 20

2.4.5

OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3)

................................................. 21

2.4.6

OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3)

............................................. 21

2.4.7

IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)

...................................................... 21

2.4.8

IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3)

......................................... 22

2.4.9

IEPBCTX_n: Input Endpoint X-Byte Base Address (n = 1 to 3)

........................................... 22

2.4.10

IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3)

......................................... 23

2.4.11

IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3)

.................................................... 23

2.4.12

IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3)

................................................ 23

2.5

Endpoint-0 Descriptor Registers

......................................................................................... 24

2.5.1

IEPCNFG_0: Input Endpoint-0 Configuration Register

..................................................... 24

2.5.2

IEPBCNT_0: Input Endpoint-0 Byte-Count Register

........................................................ 25

2.5.3

OEPCNFG_0: Output Endpoint-0 Configuration Register

................................................. 25

2.5.4

OEPBCNT_0: Output Endpoint-0 Byte-Count Register

.................................................... 26

2.6

USB Registers

.............................................................................................................. 26

2.6.1

FUNADR: Function Address Register

........................................................................ 26

2.6.2

USBSTA: USB Status Register

................................................................................ 27

2.6.3

USBMSK: USB Interrupt Mask Register

...................................................................... 28

2.6.4

USBCTL: USB Control Register

............................................................................... 28

2.6.5

VIDSTA: VID/PID Status Register

............................................................................. 29

2.7

Function Reset and Power-Up Reset Interconnect

.................................................................... 29

2.8

Pullup Resistor Connect/Disconnect

..................................................................................... 30

2.9

8052 Interrupt and Status Registers

..................................................................................... 30

2.9.1

8052 Standard Interrupt Enable Register

.................................................................... 31

2.9.2

Additional Interrupt Sources

.................................................................................... 31

2.9.3

VECINT: Vector Interrupt Register

............................................................................ 32

2.9.4

Logical Interrupt Connection Diagram (INT0)

................................................................ 33

2.9.5

P2[7:0], P3.3 Interrupt (INT1)

.................................................................................. 33

2.10

I

................................................................................................................ 34

2.10.1

I2CSTA: I

.................................................................... 34

2.10.2

I2CADR: I

................................................................................ 35

Contents

2

Submit Documentation Feedback