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Preliminary
8-130
RF2461
Rev A13 010607
8
Evaluation Board Schematic - JCDMA
LO@741MHz, RF@851MHz, IF@110MHz
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
19
18
17
16
VCC1
50
Ωµstrip
C1
33 nF
L2
16 nH
50
Ωµstrip
L1
4.3 nH
50
Ωµstrip
IF SEL
ENABLE
IP SET
C16
100 pF
50
Ωµstrip
R6
56
Ω
50
Ωµstrip
50
Ωµstrip
L8
270 nH
C15
100 pF
50
Ωµstrip
C14
7pF
50
Ωµstrip
L9
330 nH
50
Ωµstrip
R5
4.3 k
Ω
C13
9pF
C12
10 pF
C11
100 pF
50
Ωµstrip
C8
7pF
50
Ωµstrip
L6
330 nH
R4
4.3 k
Ω
C9
9pF
50
Ωµstrip
50
Ωµstrip
50
Ωµstrip
C10
11 pF
L7
270 nH
VCC1
C7
100 pF
50
Ωµstrip
R1
620
Ω
L4
7.5 nH
C5
4pF
50
Ωµstrip
C4
100 pF
C3
0.1
µF
VCC1
R2
18 k
Ω
R3
33 k
Ω
L4
7.5 nH
50
Ωµstrip
C6
33 nF
50
Ωµstrip
L5
30 nH
50
Ωµstrip
P1
1
2
3
CON3
P1-3
LNA GAIN
GND
P1-1
MIX GAIN
P2
1
2
3
CON3
P2-3
ENABLE
P2-2
IP SET
P2-1
IF SEL
P3
1
2
3
CON3
P3-1
VCC1
GND
P3-3
VCC2
VCC2
VCC1
Note: R14 improves NF and IIP3 for V
CC =3.0 V
R14
51
Ω
50
Ωµstrip
L=130 mils
W=12 mils
Z
0=50 Ω
J1
LO IN
447 pS Electrical Delay
0.13 dB Line Loss
J2
LNA IN
329 pS Electrical Delay
0.10 dB Line Loss
LNA GAIN
MIX GAIN
J3
LNA OUT
498 pS Electrical Delay
0.15 dB Line Loss
J5
IF1 OUT
348 pS Electrical Delay @ 110 MHz
0.03 dB Line Loss
J4
MIXER IN
320 pS Electrical Delay @ 880 MHz
0.10 dB Line Loss
J6
IF2 OUT
348 pS Electrical Delay @ 110 MHz
0.03 dB Line Loss
BYPASS
R14
51
Ω
C2
100 pF
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