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EP3C40 Datasheet(PDF) 20 Page - Altera Corporation

Part # EP3C40
Description  Cyclone III Device Data Sheet
PDF  34 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3C40 Datasheet(HTML) 20 Page - Altera Corporation

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Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Cyclone III Device Handbook, Volume 2
© January 2010
Altera Corporation
t
RISE
20 – 80%,
C
LOAD = 5 pF
—
500
—
—
500
—
—
500
—
ps
t
FALL
20 – 80%,
C
LOAD = 5 pF
—
500
—
—
500
—
—
500
—
ps
t
LOCK (2)
——
—
1
—
—
1
—
—
1
ms
Notes to Table 1–27:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (Note 1) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (Note 1), (2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
HSC LK (input
clock
frequency)
×10
10
—
200
10
—
155.5
10
—
155.5
MHz
×8
10
—
200
10
—
155.5
10
—
155.5
MHz
×7
10
—
200
10
—
155.5
10
—
155.5
MHz
×4
10
—
200
10
—
155.5
10
—
155.5
MHz
×2
10
—
200
10
—
155.5
10
—
155.5
MHz
×1
10
—
400
10
—
311
10
—
311
MHz
Device
operation in
Mbps
×10
100
—
400
100
—
311
100
—
311
Mbps
×8
80
—
400
80
—
311
80
—
311
Mbps
×7
70
—
400
70
—
311
70
—
311
Mbps
×4
40
—
400
40
—
311
40
—
311
Mbps
×2
20
—
400
20
—
311
20
—
311
Mbps
×1
10
—
400
10
—
311
10
—
311
Mbps
t
DUTY
—
45
—
55
45
—
5545—
55
%
TCCS
—
—
—
200
—
—
200
—
—
200
ps
Output jitter
(peak to
peak)
—
—
—
500
—
—
500
—
—
550
ps
t
RISE
20 – 80%,
C
LOAD = 5 pF
—
500
—
—
500
—
—
500
—
ps
t
FALL
20 – 80%,
C
LOAD = 5 pF
—
500
—
—
500
—
—
500
—
ps
t
LOCK (3)
——
—
1
—
—
1
—
—
1
ms
Notes to Table 1–28:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.



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