EP3C40 datasheet(27/34 Pages) ALTERA

27 / 34 page

Chapter 1: Cyclone III Device Data Sheet

1–27

I/O Timing

Altera Corporation

Cyclone III Device Handbook, Volume 2

I/O Timing

You can use the following methods to determine the I/O timing:

■

the Excel-based I/O Timing.

■

the Quartus II timing analyzer.

The Excel-based I/O Timing provides pin timing performance for each device density

and speed grade. The data is typically used prior to designing the FPGA to get a

timing budget estimation as part of the link timing analysis. The Quartus II timing

analyzer provides a more accurate and precise I/O timing data based on the specifics

of the design after place-and-route is complete.

f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices

Literature website.

Glossary

Table 1–39 lists the glossary for this chapter.

Table 1–39. Glossary (Part 1 of 5)

Letter

Term

Definitions

——

HS CLK

HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.

GCLK

Input pin directly to Global Clock network.

GCLK PLL

Input pin to Global Clock network through PLL.

HSIODR

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).

Input Waveforms

for the SSTL

Differential I/O

Standard

REF

VSWING

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