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EP3C40 Datasheet(PDF) 26 Page - Altera Corporation

Part # EP3C40
Description  Cyclone III Device Data Sheet
PDF  34 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3C40 Datasheet(HTML) 26 Page - Altera Corporation

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Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Cyclone III Device Handbook, Volume 2
© January 2010
Altera Corporation
IOE Programmable Delay
Table 1–37 and Table 1–38 list IOE programmable delay for Cyclone III devices.
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (Note 1), (2)
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
A7, I7
C6
C6
C7
C8
I7
A7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7
0
1.211
1.314
2.175
2.32
2.386
2.366
2.49
ns
Input delay from pin to
input register
Pad to I/O
input register
8
0
1.203
1.307
2.19
2.387
2.54
2.43
2.545
ns
Delay from output
register to output pin
I/O output
register to
pad
2
0
0.479
0.504
0.915
1.011
1.107
1.018
1.048
ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock
network
12
0
0.664
0.694
1.199
1.378
1.532
1.392
1.441
ns
Notes to Table 1–37:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins
(Note 1), (2)
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
A7, I7
C6
C6
C7
C8
I7
A7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7
0
1.209
1.314
2.174
2.335
2.406
2.381
2.505
ns
Input delay from pin to
input register
Pad to I/O
input register
8
0
1.207
1.312
2.202
2.402
2.558
2.447
2.557
ns
Delay from output
register to output pin
I/O output
register to
pad
2
0
0.51
0.537
0.962
1.072
1.167
1.074
1.101
ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock network
12
0
0.669
0.698
1.207
1.388
1.542
1.403
1.45
ns
Notes to Table 1–38:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software



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