Chapter 1: Cyclone III Device Data Sheet

1–25

Switching Characteristics

© January 2010

Altera Corporation

Cyclone III Device Handbook, Volume 2

Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.

Duty Cycle Distortion Specifications

Table 1–35 lists the worst case duty cycle distortion for Cyclone III devices.

OCT Calibration Timing Specification

Table 1–36 lists the duration of calibration for series OCT with calibration at device

power-up for Cyclone III devices.

QDRII SRAM

1.8 V HSTL Class I

1092

515

1092

515

1192

615

1.8 V HSTL Class II

1250

662

1250

662

1350

762

Notes to Table 1–33:

(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column

and row I/Os.

(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.

(Part 2 of 2)

Memory

Standard

I/O Standard

Column I/Os (ps)

Row I/Os (ps)

Wraparound Mode (ps)

Lead

Lag

Lead

Lag

Lead

Lag

Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (Note 1), (2)

Parameter

Symbol

Min

Max

Unit

Clock period jitter

t

JIT(per)

-125

125

ps

Cycle-to-cycle period jitter

t

JIT(cc)

-200

200

ps

Duty cycle jitter

t

JIT(duty)

-150

150

ps

Notes to Table 1–34:

(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.

(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global

clock network.

Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins

(Note 1), (2)

Symbol

C6

C7, I7

C8, A7

Unit

Min

Max

Min

Max

Min

Max

Output Duty Cycle

45

55

45

55

45

55

%

Notes to Table 1–35:

(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated

and general purpose I/O pins.

(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of

I/O standard and current strength.

Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device

Power-Up (Note 1)

Symbol

Description

Maximum

Unit

t

OCTC AL

Duration of series OCT with

calibration at device power-up

20

µs

Notes to Table 1–36:

(1) OCT calibration takes place after device configuration, before entering user mode.