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EP3C40 Datasheet(PDF) 24 Page - Altera Corporation |
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EP3C40 Datasheet(HTML) 24 Page - Altera Corporation |
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24 / 34 page  1–24 Chapter 1: Cyclone III Device Data Sheet Switching Characteristics Cyclone III Device Handbook, Volume 2 © January 2010 Altera Corporation Table 1–33 lists the transmitter channel-to-channel skew specifications for Cyclone III devices. Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (Note 1) (Part 1 of 2) Memory Standard I/O Standard Column I/Os (ps) Row I/Os (ps) Wraparound Mode (ps) Lead Lag Lead Lag Lead Lag C6 DDR2 SDRAM SSTL-18 Class I 790 380 790 380 890 480 SSTL-18 Class II 870 490 870 490 970 590 DDR SDRAM SSTL-2 Class I 750 320 750 320 850 420 SSTL-2 Class II 860 350 860 350 960 450 QDRII SRAM 1.8 V HSTL Class I 780 410 780 410 880 510 1.8 V HSTL Class II 830 510 830 510 930 610 C7 DDR2 SDRAM SSTL-18 Class I 915 410 915 410 1015 510 SSTL-18 Class II 1025 545 1025 545 1125 645 DDR SDRAM SSTL-2 Class I 880 340 880 340 980 440 SSTL-2 Class II 1010 380 1010 380 1110 480 QDRII SRAM 1.8 V HSTL Class I 910 450 910 450 1010 550 1.8 V HSTL Class II 1010 570 1010 570 1110 670 C8 DDR2 SDRAM SSTL-18 Class I 1040 440 1040 440 1140 540 SSTL-18 Class II 1180 600 1180 600 1280 700 DDR SDRAM SSTL-2 Class I 1010 360 1010 360 1110 460 SSTL-2 Class II 1160 410 1160 410 1260 510 QDRII SRAM 1.8 V HSTL Class I 1040 490 1040 490 1140 590 1.8 V HSTL Class II 1190 630 1190 630 1290 730 I7 DDR2 SDRAM SSTL-18 Class I 961 431 961 431 1061 531 SSTL-18 Class II 1076 572 1076 572 1176 672 DDR SDRAM SSTL-2 Class I 924 357 924 357 1024 457 SSTL-2 Class II 1061 399 1061 399 1161 499 QDRII SRAM 1.8 V HSTL Class I 956 473 956 473 1056 573 1.8 V HSTL Class II 1061 599 1061 599 1161 699 A7 DDR2 SDRAM (2) SSTL-18 Class I 1092 462 1092 462 1192 562 SSTL-18 Class II 1239 630 1239 630 1339 730 DDR SDRAM SSTL-2 Class I 1061 378 1061 378 1161 478 SSTL-2 Class II 1218 431 1218 431 1318 531 |
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