LM8322 datasheet(27/42 Pages) NSC

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16.7 INTERRUPT CODE

The interrupt code is read and acknowledged with the

READ_INT command (0x82). This command clears the code

and deasserts the IRQ output. Table 13 shows the format of

the interrupt code.

TABLE 13. Interrupt Code

PWM2END

PWM1END

PWM0END

NOINIT

ERROR

KEYPAD

Bit

Description

PWM2END

An END script command was executed by PWM channel 2.

PWM1END

An END script command was executed by PWM channel 1.

PWM0END

An END script command was executed by PWM channel 0.

NOINIT

The LM8322 is waiting for an initialization sequence.

ERROR

An error condition occurred.

KEYPAD

A key-press or key-release event occurred.

16.8 ERROR CODE

If the LM8322 reports an error, the READ_ERROR command

(0x8C) is used to read the error code. This command clears

the error code. Table 14 shows the format of the error code.

TABLE 14. Error Code

FIFOOVR

KEYOVR

CMDUNK

BADPAR

Bit

Description

FIFOOVER

Event occurred while the FIFO was full.

KEYOVR

More than two keys were pressed simultaneously.

CMDUNK

Not a valid command.

BADPAR

Bad command parameter.

16.9 WAKE-UP FROM HALT MODE

Any bus transaction initiated by the host may encounter the

LM8322 device in Halt mode or busy with processing data,

such as controlling the FIFO buffer or executing interrupt ser-

vice routines.

Figure 18 shows the case in which the host sends a command

while the LM8322 is in Halt mode (Internal execution clock is

stopped). Any activity on the ACCESS.bus wakes up the

LM8322, but it cannot acknowledge the first bus cycle imme-

diately after wake-up.

The host drives a Start condition followed by seven address

bits and a R/W bit. The host then releases SDA for one clock

period, so that it can be driven by the LM8322.

If the LM8322 does not drive SDA low during the high phase

of the clock period immediately after the R/W bit, the bus cycle

terminates without being acknowledged (shown as NACK in

Figure 18). The host then aborts the transaction by sending

a Stop condition. After aborting the bus cycle, the host may

then retry the bus cycle. On the second attempt, the LM8322

will be able to acknowledge the slave address, because it will

be in Active mode.

Alternatively, the I2C specification allows sending a START

byte (00000001), which will not be acknowledged by any de-

vice. This byte can be used to wake up the LM8322 from Halt

mode. The LM8322 may also stall the bus transaction by

pulling the SCL low, which is a valid behavior defined by the

I2C specification.

30013618

FIGURE 18. LM8322 Responds with NACK, Host Retries Command

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