LM8322 datasheet(10/42 Pages) NSC

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10.0 Reset

The LM8322 may be reset by either an external reset, RE-

SET command, or an internally generated power-on reset

(POR) signal. The RESET input must not be allowed to float.

If the external RESET input is not used, it must be connected

to VCC, either directly or through a pull-up resistor.

10.1 EXTERNAL RESET

The device enters a reset state immediately when the RE-

SET input is driven low. RESET must be held low for a

minimum of 700 ns to guarantee a valid reset. If RESET is

asserted at power-on, it must be held low until V

CC rises above

the minimum operating voltage (1.62V). If an RC circuit is

used to drive RESET, it must have a time constant 5 times

(5×) greater than the V

CC rise time to this level.

When RESET goes low, the I/O ports are initialized immedi-

ately, any observed delay being only propagation delay.

When the RESET pin goes high, the LM8322 comes out of

the reset state within about 1400 ns.

10.2 POWER-ON RESET (POR)

The POR circuit is always enabled. When V

CC rises above the

POR threshold voltage VPOR (about 1.2–1.5V), an on-chip

reset signal is asserted. The V

CC rise time must be greater

than 20 µs and less than 10 ms, otherwise the on-chip reset

signal may deassert before V

CC reaches the minimum oper-

ating voltage. While V

CC is below VPOR, the LM8322 is held

in reset and a timer clocked by the on-chip RC clock is preset

with 0xFF (256 clock cycles). When V

CC reaches a value

greater than VPOR, the timer starts counting down. When it

underflows, the on-chip reset signal is deasserted and the

LM8322 begins operation.

10.3 PIN CONFIGURATION AFTER RESET

Table 2 shows the pin configuration after reset.

TABLE 3. Pin Configuration After Reset

Pins

After Reset

After LM8322 Initialization

KP-X00

High-impedance mode.

Input mode with an on-chip pullup enabled.

KP-X01

KP-X02

KP-X03

High-impedance mode.

High-impedance mode, until host configures them as keypad inputs

or GPIO.

KP-X04

KP-X05

KP-X06

KP-X07

KP-Y00

High-impedance mode.

Active drive low.

KP-Y01

KP-Y02

KP-Y03

High-impedance mode.

High-impedance mode, until host configures them as keypad outputs

or GPIO.

KP-Y04

KP-Y05

KP-Y06

KP-Y07

KP-Y08

KP-Y09

KP-Y10

KP-Y11

CONFIG_1

High-impedance mode.

The ACCESS.bus slave address must be selected with external

pullup or pulldown resistors or direct connections to V

CC or GND.

CONFIG_2

IRQ

High-impedance mode.

Active drive low.

PWM_0

High-impedance mode.

PWM_1

PWM_2

ACB_SDA

Open-drain mode.

ACB_SCL

XTAL_IN

High-impedance mode.

High-impedance mode. Terminate to V

CC or GND if not used.

XTAL_OUT

Weak pullup device.

RESET

High-impedance mode.

LM8322 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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