ADUM3471ARSZ datasheet(14/32 Pages) AD

14 / 32 page

ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474

Rev. 0 | Page 14 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

*GND1 2

VDD1 3

VREG

GND2*

VDD2

VIA 5

VIB 6

VIC 7

VOA

VOB

VOC

VID 8

VOD

VDDA 9

*GND1 10

GND2*

ADuM3470

TOP VIEW

(Not to Scale)

RECOMMENDED. PIN 11 AND PIN 19 ARE

INTERNALLY CONNECTED, AND CONNECTING

BOTH TO GND2 IS RECOMMENDED.

*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED,

AND CONNECTING BOTH TO GND1 IS

Figure 4. AD

uM3470 Pin Configuration

Table 12. ADuM3470 Pin Function Descriptions

Pin No. Mnemonic Description

Transformer Driver Output 1.

2, 10

GND1

Ground 1. Ground reference for isolator primary.

VDD1

Transformer Driver Supply Voltage 3.0 V to 5.5 V. Connect to VDDA pin. Connect a 10 μF bypass capacitor from VDD1 to

GND1.

Transformer Driver Output 2.

VIA

Logic Input A.

VIB

Logic Input B.

VIC

Logic Input C.

VID

Logic Input D.

VDDA

Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1 pin. Connect a 0.1 μF bypass capacitor from VDDA to GND1.

11, 19

GND2

Ground Reference for Isolator Side 2.

Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output

voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz

to 1 MHz, as programmed by the resistor value.

VOD

Logic Output D.

VOC

Logic Output C.

VOB

Logic Output B.

VOA

Logic Output A.

Feedback Input from the Secondary Output Voltage VISO. Use a resistor divider from VISO to the FB pin to make the VFB

voltage equal to the 1.25 V internal reference level using the VISO = VFB × (R1 + R2)/R2 formula. The resistor divider is

required even in open-loop mode to provide soft start.

VDD2

The Internal Supply Voltage Pin for the Secondary Side Controller and Side 2 Data Channels. When a sufficient external

voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V

to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.

VREG

The Input of the Internal Regulator to Power the Secondary Side Controller and Side 2 Data Channels. VREG should be in

the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.

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