| Electronic Components Datasheet Search |
|
ADUM3471ARSZ Datasheet(PDF) 25 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADUM3471ARSZ Datasheet(HTML) 25 Page - Analog Devices |
|
25 / 32 page ![]() ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Rev. 0 | Page 25 of 32 APPLICATIONS INFORMATION THEORY OF OPERATION The dc-to-dc converter section of the ADuM347x uses a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. VCC power is supplied to an oscillating circuit that switches current to the primary of an external power trans- former using internal push-pull switches at the X1 and X2 pins. Power transferred to the secondary side of the transformer is full-wave rectified with external Schottky diodes (D1 and D2), filtered with the L1 inductor and COUT capacitor, and regulated to the isolated power supply voltage from 3.3 V to 15 V. The secondary (VISO) side controller regulates the output by using a feedback voltage VFB from a resistor divider on the output and creating a PWM control signal that is sent to the primary (VCC) side by a dedicated iCoupler data channel labeled VFB. The primary side PWM converter varies the duty cycle of the X1 and X2 switches to modulate the oscillator circuit and control the power being sent to the secondary side. This feedback allows for significantly higher power and efficiency. The ADuM347x implement undervoltage lockout (UVLO) with hysteresis on the VCC power input. This feature ensures that the converter does not go into oscillation due to noisy input power or slow power-on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on the output due to short or erratic PWM pulses. Excess noise generated this way can cause regulation problems, in some circumstances. APPLICATION SCHEMATICS The ADuM347x has three main application schematics, as shown in Figure 38 to Figure 40. Figure 38 has a center-tapped secondary and two Schottky diodes providing full wave rectification for a single output, typically for power supplies of 3.3 V, 5 V, 12 V, and 15 V. For single supplies when VISO = 3.3 V or VISO = 5 V, see the note in Figure 38 about connecting together VREG, VDD2, and VISO. Figure 39 is a voltage doubling circuit that can be used for a single supply whose output exceeds 15 V, which is the largest supply that can be connected to the regulator input VREG (Pin 20) of the part. With Figure 39, the output voltage can be as high as 24 V and the VREG pin only about 12 V. Figure 40, which also uses a voltage doubling secondary circuit, is shown as an example of a coarsely regulated, positive power supply and an unregulated, negative power supply, for outputs of approximately ±5 V, ±12 V, and ±15 V. For any circuit in Figure 38, Figure 39, or Figure 40, the isolated output voltage (VISO) can be set using the voltage dividers, R1 and R2 (values 1 kΩ to 100 kΩ), in the application schematics using the following equation: R2 R2 R1 V V FB ISO + × = where VFB is the internal feedback voltage, which is approximately 1.25 V. ADuM3470/ ADuM3471/ ADuM3472/ ADuM3473/ ADuM3474 1 X1 2 GND1 3 VDD1 4 X2 5 I/OA 6 I/OB 7 I/OC 8 I/OD 9 VDDA 10 GND1 20 VREG 19 GND2 18 VDD2 17 FB 16 I/OA 15 I/OB 14 I/OC 13 I/OD 12 OC 11 GND2 D1 T1 L1 COUT D2 VCC VCC 0.1µF CIN 0.1µF +5V R1 R2 ROC VFB VISO = VFB × (R1+R2)/R2 FOR VISO = 3.3V OR 5V CONNECT VREG, VDD2,AND VISO. VISO = +3.3V TO +15V 47µF 47µH 100k Ω Figure 38. Single Power Supply ADuM3470/ ADuM3471/ ADuM3472/ ADuM3473/ ADuM3474 1 X1 2 GND1 3 VDD1 4 X2 5 I/OA 6 I/OB 7 I/OC 8 I/OD 9 VDDA 10 GND1 20 VREG 19 GND2 18 VDD2 17 FB 16 I/OA 15 I/OB 14 I/OC 13 I/OD 12 OC 11 GND2 D1 T1 L1 L2 COUT1 COUT2 D2 D3 D4 VCC VCC 0.1µF CIN 0.1µF +5V R1 R2 VFB ROC VISO = VFB × (R1 + R2)/R2 FOR VISO = 15V OR LESS, VREG CAN CONNECT TO VISO. VISO = +12V TO +24V UNREGULATED +6V TO +12V 100k Ω 47µH 47µH 47µF 47µF Figure 39. Doubling Power Supply ADuM3470/ ADuM3471/ ADuM3472/ ADuM3473/ ADuM3474 1 X1 2 GND1 3 VDD1 4 X2 5 I/OA 6 I/OB 7 I/OC 8 I/OD 9 VDDA 10 GND1 20 VREG 19 GND2 18 VDD2 17 FB 16 I/OA 15 I/OB 14 I/OC 13 I/OD 12 OC 11 GND2 D1 T1 L1 L2 COUT1 COUT2 D2 D3 D4 VCC VCC 0.1µF CIN 0.1µF +5V R1 R2 ROC VFB VISO = VFB × (R1 + R2)R2 VISO = COARSELY REGULATED +5V TO 15V UNREGULATED –5V TO –15V 47µF 47µH 47µH 47µF 100k Ω Figure 40. Positive and Unregulated Negative Supply |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |