PCA88021 datasheet(6/34 Pages) NXP

6 / 34 page

PCA8802_1

Product data sheet

Rev. 01 — 19 February 2009

6 of 34

NXP Semiconductors

PCA8802

Smartcard RTC

9.1.2 Low power operation

With the power-down instruction (pwd_cmd) the oscillator can be stopped and the device

can be put into a low power state where power consumption is reduced to an absolute

minimum. The chip would normally reset when the oscillator is stopped, so to prevent a

reset of the chip during this state, a special software power-down sequence must be used

(see Table 7). In power-down state, the interface is still accessible.

A prime consideration for low power consumption is the series resistance Rs of the quartz

used. The series resistance acts as a loss element. Low Rs will reduce current

consumption further.

9.2 Divider

The divider chain is responsible for reducing the 32.768 kHz oscillator frequency down to

⁄

32 Hz.

The dividers (see Figure 7) divider_2 and divider_3 may be reset with the dvs_cmd

instruction. The 24 bit counter may be set when the dividers are held in reset, but this is

not a requirement. This allows for accurate setting and restarting of the counter.

The interface is asynchronous to the quartz oscillator and the state of divider_1 can not be

known when the dvs_cmd is enabled. The 8.192 kHz clock could have just occurred and

hence a delay of 1

⁄

8192 seconds will occur before the next increment of the divider_2, or

the 8.192 kHz clock could be just about to occur and immediately increment the divider_2.

As a consequence, an uncertainty of between zero and one 8192 Hz clock period (i.e. a

time uncertainty of about 0 s to 122

µs) will be present when restarting the counter.

VDD =3V.

Fig 6.

IDD with respect to Rs

Quartz series resistance, Rs (k

Ω)

100

001aaj165

130

170

210

250

IDD

(nA)

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