PCA88021 datasheet(7/34 Pages) NXP

7 / 34 page

PCA8802_1

Product data sheet

Rev. 01 — 19 February 2009

7 of 34

NXP Semiconductors

PCA8802

Smartcard RTC

9.3 Binary counter

A 24 bit binary roll over counter is implemented. The counter is reset at power-on.

The counter can be set to any value using the set_cmd instruction. The set_cmd

instruction allows partial writing of data. Partial writing of the data parameters will result in

partial setting of the counter, e.g. if data transfer is stopped after P1[23:16] (see Table 5)is

transmitted, then only bit 23 to bit 16 will be updated. The counter will not increment whilst

being set.

The counter can be halted by means of stopping the dividers using the dvs_cmd

instruction.

The counter can be read at any time and the counter value will remain stable during

reading. If the counter is due to increment during the read or write cycle, then the request

to increment will be held off until after the read has concluded. For this reason it is

important to read the counter in bursts, ensuring that an interface STOP condition (see

Section 9.5.4) is present between read accesses. Reading for periods of more then

32 seconds at a time will result in loss of counts.

Divider_1 = dividing by 4.

Divider_2 = dividing by 8192.

Divider_3 = dividing by 32.

Fig 7.

Divider chain

001aaj168

OSCILLATOR

STOP

DETECTOR

DIVIDER_2

DIVIDER_1

32.768 kHz

8.192 kHz

dvs_cmd - divider stop command

DIVIDER_3

1 Hz

24-BIT

COUNTER

1/32 Hz

clock

reset

power-on reset signal

clock for fast mode

(1) Increment delayed until after the read has ﬁnished.

Fig 8.

Counter behavior during read access

001aaj206

(1)

read

frozen

free

increment

free

interface state

1/32 Hz pulse

counter state

read

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