PCA88021 datasheet(10/34 Pages) NXP

10 / 34 page

PCA8802_1

Product data sheet

Rev. 01 — 19 February 2009

10 of 34

NXP Semiconductors

PCA8802

Smartcard RTC

9.5.2 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal. Bit transfer is shown in Figure 13.

9.5.3 Bit order

Data is transferred MSB ﬁrst.

9.5.4 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P). The START and STOP conditions are shown in Figure 15.

The data on SDA is sampled with the rising edge of SCL. Data is output to SDA on the

falling edge of SCL.

9.5.5 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the device which is

controlled by the master is the slave.

Fig 13. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 14. Bit transfer

001aaj212

MSB

LSB

Fig 15. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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