L7200 datasheet(27/91 Pages) INTEL

27 / 91 page

Datasheet

Electrical Specifications

NOTES:

Refer to Chapter 4, “Package Mechanical Specifications and Pin Information” for signal descriptions and

termination requirements.

In processor systems without a debug port implemented on the board, these signals are used to support

debug port interposers. In systems with the debug port implemented on the board, these signals are no

connects.

BPM[2:1]# and PRDY# are AGTL+ output only signals.

PROCHOT# signal type is open drain output and CMOS input.

On-die termination differs from other AGTL+ signals, please contact your Intel representative for more

details.

When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected.

Table 4.

FSB Pin Groups

Signal Group

Type

Signals1

AGTL+ Common Clock Input

Synchronous

to BCLK[1:0]

BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, DPWR#,

TRDY#

AGTL+ Common Clock I/O

Synchronous

to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#,

HITM#, LOCK#, PRDY#3

AGTL+ Source Synchronous I/O Synchronous

to assoc.

strobe

AGTL+ Strobes

Synchronous

to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS Input

Asynchronous

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Open Drain Output

Asynchronous FERR#, IERR#, THERMTRIP#

Open Drain I/O

Asynchronous PROCHOT#4

CMOS Output

Asynchronous PSI#, VID[6:0], BSEL[2:0]

CMOS Input

Synchronous

to TCK

TCK, TDI, TMS, TRST#

Open Drain Output

Synchronous

to TCK

TDO

FSB Clock

Clock

BCLK[1:0]

Power/Other

COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,

THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS,

VSS_SENSE

Signals

Associated Strobe

REQ[4:0]#,

A[16:3]#

ADSTB[0]#

A[35:17]#6

ADSTB[1]#

D[15:0]#, DINV0#

DSTBP0#,

DSTBN0#

D[31:16]#, DINV1#

DSTBP1#,

DSTBN1#

D[47:32]#, DINV2#

DSTBP2#,

DSTBN2#

D[63:48]#, DINV3#

DSTBP3#,

DSTBN3#

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